- 14 Oct, 2015 31 commits
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Junwei Zhang authored
The first lockup fence will lock the fence list of scheduler. Then cancel the delayed workqueues for all clean pending fences without waiting the workqueues to finish. Change-Id: I9bec826de1aa49d587b0662f3fb4a95333979429 Signed-off-by:
Junwei Zhang <Jerry.Zhang@amd.com> Reviewed-by:
Christian König <christian.koenig@amd.com>
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Junwei Zhang authored
Change-Id: I67e987db0efdca28faa80b332b75571192130d33 Signed-off-by:
David Zhou <david1.zhou@amd.com> Reviewed-by:
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Christian König authored
Output all VM mappings a command submission uses. Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Christian König authored
This makes it much easier to find when userspace misses to send some buffers. Signed-off-by:
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Christian König authored
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Christian König authored
Port of radeon commit 9b7d786b. Signed-off-by:
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Christian König authored
Signed-off-by:
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Lukas Wunner authored
This was added to two radeon files even though they don't use any vga_switcheroo symbols, the amdgpu fork inherited them: Added to amdgpu_acpi.c by commit d7a2952f ("drm/radeon: Add support for the ATIF ACPI method to the radeon driver"). Added to amdgpu_bios.c by commit 6a9ee8af ("vga_switcheroo: initial implementation (v15)"). Signed-off-by:
Lukas Wunner <lukas@wunner.de> Signed-off-by:
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Lukas Wunner authored
This was added to three files even though they don't use any vga_switcheroo symbols: Added to radeon_acpi.c by commit d7a2952f ("drm/radeon: Add support for the ATIF ACPI method to the radeon driver"). Added to radeon_asic.c by commit 0a10c851 ("drm/radeon: create radeon_asic.c"). Added to radeon_bios.c by commit 6a9ee8af ("vga_switcheroo: initial implementation (v15)"). Signed-off-by:
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Alex Deucher authored
Check to make sure we aren't touching a non-existent display controller and simplify the code. Reviewed-by:
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Alex Deucher authored
Rework the sdma structures in the driver to consolidate all of the sdma info into a single structure and allow for asics that may have different numbers of sdma instances. Reviewed-by:
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Alex Deucher authored
Everything is evicted from VRAM before suspend, so we need to make sure all BOs are unpinned and re-pinned after resume. Fixes broken mouse cursor after resume introduced by commit b9729b17. Port of radeon commit: f3cbb17bReviewed-by:
Michel Dänzer <michel.daenzer@amd.com> Signed-off-by:
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Alex Deucher authored
Port of radeon commit: 8991668aReviewed-by:
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Alex Deucher authored
Take a GEM reference for and pin the new cursor BO, unpin and drop the GEM reference for the old cursor BO in dce8 crtc_cursor_set2, and use amdgpu_crtc->cursor_addr in dce8 set_cursor. This fixes dce8 cursor_reset accidentally incrementing the cursor BO pin count, and cleans up the code a little. Port of radeon commit: cd404af0Reviewed-by:
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Alex Deucher authored
It's only needed in dce8 crtc_cursor_set2. Port of radeon commit: 2e007e61Reviewed-by:
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Alex Deucher authored
Setting a mode seems to clear the cursor registers, so we need to re-program them to make sure the cursor is visible. Port of radeon commit: 6d3759fa v2: change radeon reference in error message Reviewed-by:
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Alex Deucher authored
The cursor_set2 hook provides the cursor hotspot position within the cursor image. When the hotspot position changes, we can adjust the cursor position such that the hotspot doesn't move on the screen. This prevents the cursor from appearing to intermittently jump around on the screen when the position of the hotspot within the cursor image changes. Port of radeon commits: 78b1a601 3feba08dReviewed-by:
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Alex Deucher authored
Port of radeon commit: 8991668aReviewed-by:
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Alex Deucher authored
Take a GEM reference for and pin the new cursor BO, unpin and drop the GEM reference for the old cursor BO in dce11 crtc_cursor_set2, and use amdgpu_crtc->cursor_addr in dce11 set_cursor. This fixes dce11 cursor_reset accidentally incrementing the cursor BO pin count, and cleans up the code a little. Port of radeon commit: cd404af0Reviewed-by:
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Alex Deucher authored
It's only needed in dce11 crtc_cursor_set2. Port of radeon commit: 2e007e61Reviewed-by:
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Alex Deucher authored
Setting a mode seems to clear the cursor registers, so we need to re-program them to make sure the cursor is visible. Port of radeon commit: 6d3759fa v2: change radeon reference in error output Reviewed-by:
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Alex Deucher authored
The cursor_set2 hook provides the cursor hotspot position within the cursor image. When the hotspot position changes, we can adjust the cursor position such that the hotspot doesn't move on the screen. This prevents the cursor from appearing to intermittently jump around on the screen when the position of the hotspot within the cursor image changes. Port of radeon commits: 78b1a601 3feba08dReviewed-by:
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Alex Deucher authored
Port of radeon commit: 8991668aReviewed-by:
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Alex Deucher authored
Take a GEM reference for and pin the new cursor BO, unpin and drop the GEM reference for the old cursor BO in dce10 crtc_cursor_set2, and use amdgpu_crtc->cursor_addr in dce10 set_cursor. This fixes dce10 cursor_reset accidentally incrementing the cursor BO pin count, and cleans up the code a little. Port of radeon commit: cd404af0Reviewed-by:
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Alex Deucher authored
It's only needed in dce10 crtc_cursor_set2. Port of radeon commit: 2e007e61Reviewed-by:
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Alex Deucher authored
Setting a mode seems to clear the cursor registers, so we need to re-program them to make sure the cursor is visible. Port of radeon commit: 6d3759fa v2: change radeon reference in error message Reviewed-by:
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Alex Deucher authored
The cursor_set2 hook provides the cursor hotspot position within the cursor image. When the hotspot position changes, we can adjust the cursor position such that the hotspot doesn't move on the screen. This prevents the cursor from appearing to intermittently jump around on the screen when the position of the hotspot within the cursor image changes. Port of radeon commits: 78b1a601 3feba08dReviewed-by:
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Alex Deucher authored
Better precision than the regular div opcode. v2: drop 64 bit divide v3: fix op handling. This actually is a 64 bit divide. Reviewed-by:
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Alex Deucher authored
Better precision than the regular mul opcode. v2: handle big endian properly. Reviewed-by:
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Alex Deucher authored
Just skips a data section. Reviewed-by:
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Alex Deucher authored
Basically a nop. Reviewed-by:
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- 08 Oct, 2015 5 commits
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Alex Deucher authored
These are buggy on some asics and not really used anymore now that the GPU schedular is enabled. Change-Id: I67182b409d64de308392a15d1a0a15018071dc0b Signed-off-by: -
Chunming Zhou authored
Change-Id: Idce64f63e8422324996fc5d583d0bc9a5ac60d0c Signed-off-by:
Jammy Zhou <Jammy.Zhou@amd.com> Reviewed-by:
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Chunming Zhou authored
need to decrease visible vram usage by default. Signed-off-by:
monk.liu <monk.liu@amd.com> Reviewed-by:
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Chunming Zhou authored
Signed-off-by:
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Alex Deucher authored
Calculate the driver state in sw_init and program the registers in hw init. Acked-by:
Leo Liu <leo.liu@amd.com> Reviewed-by:
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- 02 Oct, 2015 4 commits
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Grazvydas Ignotas authored
There doesn't seem to be any need to have 'ib' volatile, the code is not even consistent with it and some places already miss it. As it is now it's just making gcc produce worse code. If there are special requirements for that memory, then proper primitives like memory barriers or accessor functions should be used, but it doesn't look like that is needed here. While at it, change the type to match the one in radeon_ib structure. Reviewed-by:
Dave Airlie <airlied@redhat.com> Signed-off-by:
Grazvydas Ignotas <notasas@gmail.com> Signed-off-by:
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Grazvydas Ignotas authored
After this patch the register check loop does the same thing as before, except that now gcc does better job optimizing it: it now sees that end_reg was already checked against PACKET3_SET_CONTEXT_REG_END and can optimize REG_SAFE_BM_SIZE comparison out of evergreen_is_safe_reg() as (PACKET3_SET_CONTEXT_REG_END >> 7) < REG_SAFE_BM_SIZE. Reviewed-by:
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Grazvydas Ignotas authored
evergreen_cs_check_reg() is a large function and gcc doesn't want to inline it. It has a quick check for reg_safe_bm[] to see if register needs special handling, which often results in early exit. However because the function is large, it has a long prologue/epilogue to save/restore all the callee-save registers which according to perf is taking significant amount of time. To avoid this, we can reuse evergreen_is_safe_reg() to do the early check directly in register loop. Reviewed-by:
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Grazvydas Ignotas authored
To avoid having to distinguish between CAYMAN or older on every register check, place a pointer in evergreen_cs_track and use it unconditionally. Also make use of the fact that both reg_safe_bm[] arrays are of the same length to remove another CAYMAN check. Reviewed-by:
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