- 23 Aug, 2019 14 commits
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Josip Pavic authored
[Why] ABM 2.3 firmware expects information in iRAM that differs from previous versions of ABM, so a mechanism is required to provide it with that information. [How] Extend the existing iRAM definition to include parameters added by ABM 2.3, and load it if DMCU is running ABM 2.3. Signed-off-by:
Josip Pavic <Josip.Pavic@amd.com> Reviewed-by:
Anthony Koo <Anthony.Koo@amd.com> Acked-by:
Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Zi Yu Liao authored
[why] With Scatter Gather enabled, HUBP underflows during MPO enabled video playback. hubp_init has a register write that fixes this problem, but the register is cleared when HUBP gets power gated. [how] Make a call to hubp_init during enable_plane, so that the fix can be applied after HUBP powers back on again. Signed-off-by:
Zi Yu Liao <ziyu.liao@amd.com> Reviewed-by:
Tony Cheng <Tony.Cheng@amd.com> Acked-by:
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Su Sung Chung authored
[Why] Disable_audio_stream gets enum option as a paramenter which will decide if we free acquired resources or not. However checks for the option is guarded by the other condition which check if audio stream is getting diabled more than once. With both conditions combined, if we attempt to disable audio stream twice in a row, first with keep and second with free as an option, we will never free any resources, which will make system think there is audio endpoint connected even after we plug out the device [How] Get rid of option as parameter to disable_audio_stream and move the part of the code that free acquired resources to outside where to keep or to free resources is actually determined Signed-off-by:
Su Sung Chung <Su.Chung@amd.com> Reviewed-by:
Jun Lei <Jun.Lei@amd.com> Acked-by:
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Julian Parkin authored
[Why] dig_encoder_sel_to_atom will always return zero on any ASIC version past DCE80 since programming of the FE selection is handled by driver, but the translation code was left in the function, making it look like a coding error. [How] Remove code that has no effect, and replace with a comment describing why it returns zero. Signed-off-by:
Julian Parkin <julian.parkin@amd.com> Reviewed-by:
Wenjing Liu <Wenjing.Liu@amd.com> Acked-by:
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Dmytro Laktyushkin authored
Currently odm is handled using top_bottom pipe by special casing the differing opps to differentiate from mpc combine. Since top/bottom pipe list was made to track mpc muxing this creates difficulties in adding a 4 pipe odm case support. Rather than continue using mpc combine list, this change reworks odm to use it's own linked list to keep track of odm combine pipes. This also opens up options for using mpo with odm, if a practical use case is ever found. Signed-off-by:
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by:
Charlene Liu <Charlene.Liu@amd.com> Acked-by:
Leo Li <sunpeng.li@amd.com> Signed-off-by:
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Alex Deucher authored
So that we properly handle them on older asics. Fixes: 3ff98548 ("drm/amdgpu: Export function to flush TLB of specific vm hub") Tested-by:
Tom St Denis <tom.stdenis@amd.com> Reviewed-by:
Xiaojie Yuan <xiaojie.yuan@amd.com> Signed-off-by:
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Alex Deucher authored
Add a dcfeaturemask flag for mclk switching. Disable by default; enable once the feature has seen more testing. Set amdgpu.dcfeaturemask=2 on the kernel command line in grub to enable this. Acked-by:
Evan Quan <evan.quan@amd.com> Reviewed-by:
Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by:
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Alex Deucher authored
Properly set all_displays_in_sync so that when the data is propagated to powerplay, it's set properly and we can enable mclk switching when all monitors are in sync. v2: fix logic, clean up v3: check for blending chains, simplify logic Acked-by:
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Alex Deucher authored
If DC has synced the displays, we can enable mclk switching to save power. Reviewed-by:
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Alex Deucher authored
If DC has synced the displays, we can enable mclk switching to save power. Reviewed-by:
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Kent Russell authored
For the 40.46 SMU release, they changed CurrSocketPower to AverageSocketPower, but this was changed back in 40.47 so just check if it's 40.46 and make the appropriate change Tested with 40.45, 40.46 and 40.47 successfully Signed-off-by:
Kent Russell <kent.russell@amd.com> Reviewed-by:
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Frank.Min authored
Add the virtual function PCI device id. Reviewed-by:
Frank.Min <Frank.Min@amd.com> Signed-off-by:
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Kevin Wang authored
fix other navi asic set peak performance level error. because the navi10_ppt.c will handle navi12 14 asic, it will use navi10 peak value to set other asic, it is not correct. after patch: only navi10 use custom peak value, other asic will used default value. Signed-off-by:
Kevin Wang <kevin1.wang@amd.com> Reviewed-by:
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Guchun Chen authored
Use unsigned long type for the same ras count variable. This will avoid overflow on 64 bit system. Signed-off-by:
Guchun Chen <guchun.chen@amd.com> Reviewed-by:
Tao Zhou <tao.zhou1@amd.com> Signed-off-by:
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- 22 Aug, 2019 26 commits
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Dmytro Laktyushkin authored
This was broken by a previous change switching to cached fw_info. Fixed by inverting a valid bool check. Bug: https://bugs.freedesktop.org/show_bug.cgi?id=111432 Fixes: 9adc8050 ("drm/amd/display: make firmware info only load once during dc_bios create") Signed-off-by:
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Thong Thai authored
This will enable indirect SRAM loading for VCN DPG mode initialization. Signed-off-by:
Thong Thai <thong.thai@amd.com> Reviewed-by:
Leo Liu <leo.liu@amd.com> Reviewed-by:
Prike Liang <Prike.Liang@amd.com> Signed-off-by:
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Thong Thai authored
This reverts commit 444a0fea. We are ready to enable it now. Signed-off-by:
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Aaron Liu authored
This patch updates gc/sdma goldensetting for renoir Signed-off-by:
Aaron Liu <aaron.liu@amd.com> Reviewed-by:
Huang Rui <ray.huang@amd.com> Signed-off-by:
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Prike Liang authored
To avoid the dpm frequence range get failed when DPM enabled and it will be enabled later once handle well the feature bit map struct. Signed-off-by:
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Prike Liang authored
enable the dpm feature for the renoir. Signed-off-by:
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Prike Liang authored
Enable SDMA PG flag during device ip early init. Reviewed-by:
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Prike Liang authored
Add support for SDMA clockgating on RN. Signed-off-by:
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Prike Liang authored
setup mmhub clockgating. Signed-off-by:
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Prike Liang authored
Enable DF clock gating during DF IP early init. Signed-off-by:
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Prike Liang authored
Enable athub MG and LS clock gating. Signed-off-by:
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Prike Liang authored
Enable IH clock gating during IH block initialized. Signed-off-by:
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Prike Liang authored
Enable VCN middle grain clock gating. Signed-off-by:
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Prike Liang authored
Enable rom light sleep clock gating. Reviewed-by:
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Prike Liang authored
Enable HDP light sleep clock gating. Signed-off-by:
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Prike Liang authored
Enable BIF light sleep clock gating. Signed-off-by:
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Prike Liang authored
Enable sdma middle grain and light sleep clock gating. Signed-off-by:
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Prike Liang authored
Enable mmhub midle grain and light sleep clock gating. Signed-off-by:
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Prike Liang authored
Enable gfx cg/mg/cp etc clock gating. Signed-off-by:
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Aaron Liu authored
This patch adds add DPMCLOCKS table implementation Rename smu_populate_smc_pptable to smu_populate_smc_tables Signed-off-by:
Kenneth Feng <kenneth.feng@amd.com> Reviewed-by:
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Aaron Liu authored
Initialize smu tables for renoir: WATERMARKS/DPMCLOCKS/SMU_METRICS Signed-off-by:
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Aaron Liu authored
add and map smu tables for renoir Signed-off-by:
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Aaron Liu authored
Check whether the message mapping is valid Signed-off-by:
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Aaron Liu authored
For renoir, it should use mmSMUIO_GFX_MISC_CNTL to check gfxoff status. For the first time to enter gfxoff status, it maybe takes about one second more. So just set the max timeout to 5s. GFXOFF_STATUS(bits 2:1)'s description is below: 0=GFXOFF(default). 1=Transition out of GFX State. 2=Not in GFXOFF. 3=Transition into GFXOFF. Reviewed-by:
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Aaron Liu authored
This patch updates gfxoff feature. Signed-off-by:
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Aaron Liu authored
add set_gfx_cgpg implement v2: check if using sw_smu (Alex) Signed-off-by:
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