- 07 May, 2021 1 commit
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Dave Airlie authored
Merge tag 'drm-intel-next-fixes-2021-04-30' of git://anongit.freedesktop.org/drm/drm-intel into drm-next drm/i915 GVT fixes for v5.13-rc1: - Fix a possible division by zero in vgpu display rate calculation Signed-off-by:
Dave Airlie <airlied@redhat.com> From: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/87wnsk16sa.fsf@intel.com
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- 30 Apr, 2021 3 commits
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Dave Airlie authored
Merge tag 'drm-intel-next-fixes-2021-04-27' of git://anongit.freedesktop.org/drm/drm-intel into drm-next drm/i915 fixes for v5.13-rc1: - Several fixes to GLK handling in recent display refactoring (Ville) - Rare watchdog timer race fix (Tvrtko) - Cppcheck redundant condition fix (José) - Overlay error code propagation fix (Dan Carpenter) - Documentation fix (Maarten) Signed-off-by:
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Dave Airlie authored
Merge tag 'amd-drm-next-5.13-2021-04-23' of https://gitlab.freedesktop.org/agd5f/linux into drm-next amd-drm-next-5.13-2021-04-23: amdgpu: - Fixes for Aldebaran - Display LTTPR fixes - eDP fixes - Fixes for Vangogh - RAS fixes - ASPM support - Renoir SMU fixes - Modifier fixes - Misc code cleanups - Freesync fixes Signed-off-by:
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Dave Airlie authored
Merge tag 'drm-misc-next-fixes-2021-04-29' of git://anongit.freedesktop.org/drm/drm-misc into drm-next Two patches in drm-misc-next-fixes this week, one to fix the error handling in TTM when a BO can't be swapped out and one to prevent a wrong dereference in efifb. Signed-off-by:
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- 29 Apr, 2021 3 commits
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ssh://git.freedesktop.org/git/tegra/linuxDave Airlie authored
drm/tegra: Changes for v5.13-rc1 The changes this time around contain a couple of fixes for host1x along with some improvements for Tegra DRM. Most notably the Tegra DRM driver now supports the hardware cursor on Tegra186 and later, more correctly reflects the capabilities of the display pipelines on various Tegra SoC generations and knows how to deal with the dGPU sector layout by using framebuffer modifiers. Signed-off-by:
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https://github.com/intel/gvt-linuxJani Nikula authored
Merge tag 'gvt-next-fixes-2021-04-29' of https://github.com/intel/gvt-linux into drm-intel-next-fixes gvt-next-fixes-2021-04-29 - Fix possible divide error in vgpu display rate calculation (Colin) Signed-off-by:
Jani Nikula <jani.nikula@intel.com> From: Zhenyu Wang <zhenyuw@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210429085142.GT1551@zhen-hp.sh.intel.com
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Colin Xu authored
To get refresh rate as vblank timer period and keep the precision, the calculation of rate is multiplied by 1000. However old logic was using: rate = pixel clock / (h * v / 1000). When the h/v total is invalid, like all 0, h * v / 1000 will be rounded to 0, which leads to a divided by 0 fault. 0 H/V are already checked above. Instead of divide after divide, refine the calculation to divide after multiply: "pixel clock * 1000 / (h * v)" Guest driver should guarantee the correctness of the timing regs' value. Fixes: 6a4500c7 ("drm/i915/gvt: Get accurate vGPU virtual display refresh rate from vreg") Reported-by:
Zhenyu Wang <zhenyuw@linux.intel.com> Signed-off-by:
Colin Xu <colin.xu@intel.com> Signed-off-by:
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- 26 Apr, 2021 8 commits
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Kai-Heng Feng authored
On some platforms like Hyper-V and RPi4 with UEFI firmware, efifb is not a PCI device. So make sure efifb_pci_dev is found before using it. Fixes: a6c0fd3d ("efifb: Ensure graphics device for efifb stays at PCI D0") BugLink: https://bugs.launchpad.net/bugs/1922403Signed-off-by:
Kai-Heng Feng <kai.heng.feng@canonical.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com> Reviewed-by:
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Maarten Lankhorst authored
Fixes the following htmldocs warning: drivers/gpu/drm/i915/gem/i915_gem_shrinker.c:102: warning: Function parameter or member 'ww' not described in 'i915_gem_shrink' Fixes: cf41a8f1 ("drm/i915: Finally remove obj->mm.lock.") Reported-by:
Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by:
Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210421120938.546076-1-maarten.lankhorst@linux.intel.comReviewed-by:
Daniel Vetter <daniel.vetter@ffwll.ch> (cherry picked from commit 772f7bb7) Signed-off-by:
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Dan Carpenter authored
This code should propagate the error from intel_overlay_pin_fb() but currently it returns success. Fixes: 1b321026 ("drm/i915: Pass ww ctx to intel_pin_to_display_plane") Signed-off-by:
Dan Carpenter <dan.carpenter@oracle.com> Reviewed-by:
Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by:
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José Roberto de Souza authored
Fix redundant condition, caught in cppcheck by kernel test robot. Reported-by:
kernel test robot <lkp@intel.com> Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com> Fixes: b64d6c51 ("drm/i915/display: Support PSR Multiple Instances") Signed-off-by:
José Roberto de Souza <jose.souza@intel.com> Reviewed-by:
Harish Chegondi <harish.chegondi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210409231738.238682-1-jose.souza@intel.com (cherry picked from commit 1884b579) Signed-off-by:
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Ville Syrjälä authored
The glk display version change is causing us to again attempt LTTPR detection on glk. We must not do tha since glk doesn't have a long enough AUX timeout. Restore the correct logic to skip the detection. Cc: Matt Roper <matthew.d.roper@intel.com> Fixes: 2b5a4562 ("drm/i915/display: Simplify GLK display version tests") Reviewed-by:
Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by:
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Ville Syrjälä authored
We lost a CCS related w/a on glk when the display version became 10 instead of 9. Restore the correct check. Cc: Matt Roper <matthew.d.roper@intel.com> Fixes: 2b5a4562 ("drm/i915/display: Simplify GLK display version tests") Reviewed-by:
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Ville Syrjälä authored
We lost the FBC 16bpp 512byte stride requirement on glk when we switched from display version 9 to 10. Restore the w/a to avoid enabling FBC with a bad stride and thus display garbage. Cc: Matt Roper <matthew.d.roper@intel.com> Fixes: 2b5a4562 ("drm/i915/display: Simplify GLK display version tests") Reviewed-by:
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Tvrtko Ursulin authored
Reference needs to be taken before arming the timer. Luckily, given the default timer period of 20s, the potential to hit the race is extremely unlikely. Signed-off-by:
Tvrtko Ursulin <tvrtko.ursulin@intel.com> Fixes: 9b4d0598 ("drm/i915: Request watchdog infrastructure") Cc: Daniel Vetter <daniel.vetter@ffwll.ch> Reviewed-by:
Mika Kuoppala <mika.kuoppala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210326105759.2387104-1-tvrtko.ursulin@linux.intel.com (cherry picked from commit f7c37977) Signed-off-by:
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- 23 Apr, 2021 2 commits
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Shiwu Zhang authored
In case that all pre-allocated BOs are busy, just continue to populate BOs since likely half of system memory in total is still free. v4 (chk): fix code moved to VMWGFX as well Signed-off-by:
Shiwu Zhang <shiwu.zhang@amd.com> Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
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Dave Airlie authored
Merge tag 'drm-misc-next-fixes-2021-04-22' of git://anongit.freedesktop.org/drm/drm-misc into drm-next A few fixes for the next merge window, with some build fixes for anx7625 and lt8912b bridges, incorrect error handling for lt8912b and TTM, and one fix for TTM page limit accounting. Signed-off-by:
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- 21 Apr, 2021 23 commits
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Felix Kuehling authored
Pages in SG BOs were not allocated by TTM. So don't count them against TTM's pages limit. Signed-off-by:
Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by:
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Christian König authored
The function returns the number of swapped pages here. Only abort when we get a negative error code. Signed-off-by:
Matthew Auld <matthew.auld@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210409130113.1459-1-christian.koenig@amd.com
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https://github.com/intel/gvt-linuxJani Nikula authored
Merge tag 'gvt-next-fixes-2021-04-21' of https://github.com/intel/gvt-linux into drm-intel-next-fixes gvt-next-fixes-2021-04-21 - Remove one unused function warning (Jiapeng) - Fix intel_gvt_init_device() return type (Dan) - Remove one duplicated register accessible check (Zhenyu) Signed-off-by:
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Zhenyu Wang authored
Looks this duplication was missed in code rebase. Remove extra check. Cc: Yan Zhao <yan.y.zhao@intel.com> Fixes: 02dd2b12 ("drm/i915/gvt: unify lri cmd handler and mmio handlers") Reviewed-by:
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Alex Deucher authored
Aldebaran has a hw fix so no longer requires the workaround. Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
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Jinzhou Su authored
The buffer of SA bo will be used by many cases. So it's better to invalidate the cache of indirect buffer allocated by SA before commit the IB. Signed-off-by:
Jinzhou Su <Jinzhou.Su@amd.com> Reviewed-by:
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Mukul Joshi authored
Fix the following issues with SDMA RAS error reporting: 1. Read the EDC_COUNTER2 register also to fetch error counts for all sub-blocks in SDMA. 2. SDMA RAS on Aldebaran suports single-bit uncorrectable errors only. So, report error count in UE count instead of CE count. Signed-off-by:
Mukul Joshi <mukul.joshi@amd.com> Reviewed-By:
John Clements <John.Clements@amd.com> Signed-off-by:
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Mukul Joshi authored
Reset the RAS error count and error status registers after reading to prevent over reporting error counts on Aldebaran. Signed-off-by:
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Oak Zeng authored
This reverts commit 2f055097. 2f055097 was a driver workaround when PSP firmware was not ready. Now the PSP fw is ready so we revert this driver workaround. Signed-off-by:
Oak Zeng <Oak.Zeng@amd.com> Reviewed-by:
Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com> Signed-off-by:
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Aric Cyr authored
Signed-off-by:
Aric Cyr <aric.cyr@amd.com> Acked-by:
Aurabindo Pillai <aurabindo.pillai@amd.com> Tested-by:
Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by:
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Anthony Koo authored
Signed-off-by:
Anthony Koo <Anthony.Koo@amd.com> Acked-by:
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Bing Guo authored
[Why] Some MST devices uses different method to enable mst specific stream features. [How] Add dm_helpers_mst_enable_stream features. This can be modified later when we are ready to implement those features. Signed-off-by:
Bing Guo <bing.guo@amd.com> Reviewed-by:
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Dillon Varone authored
[Why?] When a monitor does not set both QS and QY bits, DC does not set Q0, Q1, QY0 and QY1 bits in AVI infoframe. Setting RGB bits should be separate from setting YCC bits. [How?] Separate logic for setting RGB and YCC quantization range bits in the AVI infoframe. Signed-off-by:
Dillon Varone <dillon.varone@amd.com> Reviewed-by:
Chris Park <Chris.Park@amd.com> Acked-by:
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Dillon Varone authored
[Why & How?] Call to dc_dsc_compute_bandwidth_range should have min and max bpp in 16ths of a bit. Multiply min and max bpp from policy. Signed-off-by:
Eryk Brol <Eryk.Brol@amd.com> Acked-by:
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David Galiffi authored
[How & Why] Changed "prsent" to "present". Signed-off-by:
David Galiffi <David.Galiffi@amd.com> Reviewed-by:
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Nicholas Kazlauskas authored
[Why] Requirement from the spec - we shouldn't be potentially exiting out early based on encryption status. [How] Drop the calls from HDCP1 and HDCP2 execution that exit out early based on link encryption status. Signed-off-by:
Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Reviewed-by:
Wenjing Liu <Wenjing.Liu@amd.com> Acked-by:
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Michael Strauss authored
[Why&How] Add logs to verify ILR optimization behaviour on boot Signed-off-by:
Michael Strauss <michael.strauss@amd.com> Reviewed-by:
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Wesley Chalmers authored
[WHY] While Link Training is being performed, and the LTTPRs are in Non-LTTPR or LTTPR Transparent mode, any DPCD registers besides those used for Link Training are not to be accessed. The spec defines the link training registers as DP_TRAINING_PATTERN_SET (102h) to DP_TRAINING_LANE3_SET (106h), and DP_LANE0_1_STATUS (202h) to DP_ADJUST_REQUEST_LANE2_3 (207h). [HOW] Move the current write to DPCD Address DP_LINK_TRAINING_PATTERN_SET out of its conditional block. Signed-off-by:
Wesley Chalmers <Wesley.Chalmers@amd.com> Reviewed-by:
Jun Lei <Jun.Lei@amd.com> Acked-by:
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Aric Cyr authored
[WHY] We should skip programming manual trigger on non-primary planes when MPO is enabled. [HOW] Implement an explicit mechanism for skipping manual trigger programming for planes that shouldn't cause the frame to end. Signed-off-by:
Krunoslav Kovac <Krunoslav.Kovac@amd.com> Tested-by:
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Hugo Hu authored
Previous change had been reverted since it caused hang. Remake change to avoid defect. [Why] 1. Driver use umachannelnumber to calculate watermarks for stutter. In asymmetric memory config, the actual bandwidth is less than dual-channel. The bandwidth should be the same as single-channel. 2. We found single rank dimm need additional delay time for stutter. [How] Get information from each DIMM. Treat memory config as a single-channel for asymmetric memory in bandwidth calculating. Add additional delay time for single rank dimm. Fixes: b8720ed0 ("drm/amd/display: System black screen hangs on driver load") Signed-off-by:
Hugo Hu <hugo.hu@amd.com> Reviewed-by:
Sung Lee <Sung.Lee@amd.com> Acked-by:
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Robin Singh authored
[Why] Found that dc_link_reallocate_mst_payload is not used anymore in any of the use case scenario. [How] removed dc_link_reallocate_mst_payload function definition and declaration. Signed-off-by:
Robin Singh <robin.singh@amd.com> Reviewed-by:
Harry Wentland <Harry.Wentland@amd.com> Acked-by:
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Anthony Wang authored
[Why] Primary feature use case is with eDP panels. [How] Fail seamless boot validation if display is not an eDP panel. Signed-off-by:
Anthony Wang <anthony1.wang@amd.com> Reviewed-by:
Martin Leung <Martin.Leung@amd.com> Acked-by:
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Dingchen (David) Zhang authored
[why] the current implementation of hdcp2 rx id list validation does not have handler/checker for invalid message status, e.g. HMAC, the V parameter calculated from PSP not matching the V prime from Rx. [how] return a generic FAILURE for any message status not SUCCESS or REVOKED. Signed-off-by:
Dingchen (David) Zhang <dingchen.zhang@amd.com> Reviewed-by:
Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Acked-by:
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