- 09 Apr, 2021 2 commits
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Marijn Suijten authored
Neither vtotal nor drm_mode_vrefresh contain a value that is premultiplied by 100 making the x100 variable name incorrect and resulting in vclks_line to become 100 times larger than it is supposed to be. The hardware counts 100 clockticks too many before tearcheck, leading to severe panel issues on at least the Sony Xperia lineup. This is likely an artifact from the original MDSS DSI panel driver where the calculation [1] corrected for a premultiplied reference framerate by 100 [2]. It does not appear that the above values were ever premultiplied in the history of the DRM MDP5 driver. With this change applied the value written to the SYNC_CONFIG_VSYNC register is now identical to downstream kernels. [1]: https://source.codeaurora.org/quic/la/kernel/msm-3.18/tree/drivers/video/msm/mdss/mdss_mdp_intf_cmd.c?h=LA.UM.8.6.c26-02400-89xx.0#n288 [2]: https://source.codeaurora.org/quic/la/kernel/msm-3.18/tree/drivers/video/msm/mdss/mdss_dsi_panel.c?h=LA.UM.8.6.c26-02400-89xx.0#n1648Reviewed-by:
AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Signed-off-by:
Marijn Suijten <marijn.suijten@somainline.org> Link: https://lore.kernel.org/r/20210406214726.131534-3-marijn.suijten@somainline.orgSigned-off-by:
Rob Clark <robdclark@chromium.org>
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Marijn Suijten authored
Leaving this at a close-to-maximum register value 0xFFF0 means it takes very long for the MDSS to generate a software vsync interrupt when the hardware TE interrupt doesn't arrive. Configuring this to double the vtotal (like some downstream kernels) leads to a frame to take at most twice before the vsync signal, until hardware TE comes up. In this case the hardware interrupt responsible for providing this signal - "disp-te" gpio - is not hooked up to the mdp5 vsync/pp logic at all. This solves severe panel update issues observed on at least the Xperia Loire and Tone series, until said gpio is properly hooked up to an irq. Suggested-by:
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- 07 Apr, 2021 38 commits
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Krishna Manikandan authored
Some irqs which are applicable for sdm845 target are no longer applicable for sc7180 and sc7280 targets. Add a flag to indicate the irqs which are obsolete for a particular target so that these irqs are skipped while checking for matching irq lookup index. Signed-off-by:
Krishna Manikandan <mkrishn@codeaurora.org> Link: https://lore.kernel.org/r/1617688895-26275-4-git-send-email-mkrishn@codeaurora.orgSigned-off-by:
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Krishna Manikandan authored
INTF_5 is used by EDP panel in SC7280 target. Add vsync and underrun irqs needed by INTF_5 to dpu irq map. Signed-off-by:
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Krishna Manikandan authored
Currently, each register in the dpu interrupt set is allowed to have a maximum of 32 interrupts. With the introduction of INTF_5_VSYNC and INTF_5_UNDERRUN irqs for EDP panel, the total number of interrupts under INTR_STATUS register in dpu_irq_map will exceed 32. Increase the range of each interrupt register to 64 to handle this. This patch has dependency on the below series: https://patchwork.kernel.org/project/linux-arm-msm/list/?series=461193Signed-off-by:
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Krishna Manikandan authored
The reset value of INTF_CONFIG2 register is changed for SC7280 family. Changes are added to program this register correctly based on the target. DATA_HCTL_EN in INTF_CONFIG2 register allows data to be transferred at a different rate than video timing. When this is set, the number of data per line follows DISPLAY_DATA_HCTL register value. This change adds support to program these registers for sc7280 target. Signed-off-by:
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Krishna Manikandan authored
A new register called CTL_FETCH_ACTIVE is introduced in SC7280 family which is used to inform the HW about the pipes which are active in the current ctl path. This change adds support to program this register based on the active pipes in the current composition. Signed-off-by:
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Krishna Manikandan authored
Interface block offsets are different for SC7280 family when compared to existing targets. These offset values are used to access the interface irq registers. This change adds proper interface offsets for SC7280 target. Signed-off-by:
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Krishna Manikandan authored
Add required display hw catalog changes for SC7280 target. Signed-off-by:
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Rob Clark authored
Now that tracking is wired up for potentially evictable GEM objects, wire up shrinker and the remaining GEM bits for unpinning backing pages of inactive objects. Disabled by default for now, with an 'enable_eviction' module param to enable so that we can get some more testing on the range of generations (and iommu pairings) supported. Signed-off-by:
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Rob Clark authored
Shoot down any mmap's *first* before put_pages(). Also add a WARN_ON that the object is locked (to make it clear that this doesn't race with msm_gem_fault()) and remove a redundant WARN_ON (since is_purgable() already covers that case). Fixes: 68209390 ("drm/msm: shrinker support") Signed-off-by:
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Rob Clark authored
Objects that are potential for swapping out are (1) willneed (ie. if they are purgable/MADV_WONTNEED we can just free the pages without them having to land in swap), (2) not on an active list, (3) not dma-buf imported or exported, and (4) not vmap'd. This repurposes the purged list for objects that do not have backing pages (either because they have not been pinned for the first time yet, or in a later patch because they have been unpinned/evicted. Signed-off-by:
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Rob Clark authored
Currently nearly everything, other than newly allocated objects which are not yet backed by pages, is pinned and resident in RAM. But it will be nice to have some stats on what is unpinned once that is supported. Signed-off-by:
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Rob Clark authored
Currently these always go together, either when we purge MADV_WONTNEED objects or when the object is freed. But for unpin, we want to be able to purge (unmap from iommu) the vma, while keeping the iova range allocated (so we can remap back to the same GPU virtual address when the object is re-pinned. Signed-off-by:
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Rob Clark authored
Currently this doesn't matter since we keep the pages pinned until the object is destroyed. But when we start unpinning pages to allow objects to be evicted to swap, it will. Signed-off-by:
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Rob Clark authored
So we don't have to duplicate the boilerplate for eviction. This also lets us re-use the main scan loop for vmap shrinker. Signed-off-by:
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Rob Clark authored
If you mess something up, you don't really need to see the same warn on splat 4000 times pumped out a slow debug UART port.. Signed-off-by:
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Dmitry Baryshkov authored
Currently DPU driver scales bandwidth and core clock for sc7180 only, while the rest of chips get static bandwidth votes. Make all chipsets scale bandwidth and clock per composition requirements like sc7180 does. Drop old voting path completely. Tested on RB3 (SDM845) and RB5 (SM8250). Signed-off-by:
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20210401020533.3956787-2-dmitry.baryshkov@linaro.orgSigned-off-by:
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Dmitry Baryshkov authored
Fill clk_inefficiency_factor, bw_inefficiency_factor and min_prefill_lines in hw catalog data for sdm845 and sm8[12]50. Efficiency factors are blindly copied from sc7180 data, while min_prefill_lines is based on downstream display driver. Signed-off-by:
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Dmitry Baryshkov authored
SM8250 platform has a 8-Levels VIG QoS setting. This setting was missed due to bad interaction with b8dab65b ("drm/msm/dpu: Move DPU_SSPP_QOS_8LVL bit to SDM845 and SC7180 masks"), which was applied in parallel. Fixes: d21fc5df ("drm/msm/dpu1: add support for qseed3lite used on sm8250") Signed-off-by:
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Dmitry Baryshkov authored
Phy driver already knows the source PLL id basing on the set usecase and the current PLL id. Stop passing it to the phy_enable call. As a reminder, dsi manager will always use DSI 0 as a clock master in a slave mode, so PLL 0 is always a clocksource for DSI 0 and it is always a clocksource for DSI 1 too unless DSI 1 is used in the standalone mode. Signed-off-by:
Abhinav Kumar <abhinavk@codeaurora.org> Link: https://lore.kernel.org/r/20210331105735.3690009-25-dmitry.baryshkov@linaro.orgSigned-off-by:
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Dmitry Baryshkov authored
The src_truthtable config is not used for some of phys, which use other means of configuring the master/slave usecases. Inline this function with the goal of removing src_pll_id argument in the next commit. Signed-off-by:
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Dmitry Baryshkov authored
The 7nm, 10nm and 14nm drivers would store interim data used during VCO/PLL rate setting in the global dsi_pll_Nnm structure. Move this data structures to the onstack storage. While we are at it, drop unused/static 'config' data, unused config fields, etc. Signed-off-by:
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Dmitry Baryshkov authored
Drop duplicate fields pdev and id from dsi_pll_Nnm instances. Reuse those fields from the provided msm_dsi_phy. Signed-off-by:
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Dmitry Baryshkov authored
All PHY drivers would map dsi_pll area. Some PHY drivers would also map dsi_phy area again (a leftover from old PHY/PLL separation). Move all ioremaps to the common dsi_phy driver code and drop individual ioremapped areas from PHY drivers. Signed-off-by:
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Dmitry Baryshkov authored
Replace PLL accessor functions (pll_read/pll_write*) with the DSI PHY accessors, reducing duplication. Signed-off-by:
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Dmitry Baryshkov authored
Drop the struct msm_dsi_pll abstraction, by including vco's clk_hw directly into struct msm_dsi_phy. Signed-off-by:
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Dmitry Baryshkov authored
Make save_state/restore callbacks accept struct msm_dsi_phy rather than struct msm_dsi_pll. This moves them to struct msm_dsi_phy_ops, allowing us to drop struct msm_dsi_pll_ops. Signed-off-by:
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Dmitry Baryshkov authored
10nm and 7nm already do not use these helpers, as they handle setting slave DSI clocks after enabling VCO. Modify the rest of PHY drivers to remove unnecessary indirection and drop enable_seq/disable_seq PLL callbacks. Signed-off-by:
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Dmitry Baryshkov authored
Instead of setting the variable and then using it just in the one place, determine vco_delay directly at the PLL configuration time. Signed-off-by:
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Dmitry Baryshkov authored
These drivers do not use vco_delay variable, so drop it from all of them. Signed-off-by:
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Dmitry Baryshkov authored
Morph msm_dsi_pll_save/restore_state() into msm_dsi_phy_save/restore_state(), thus removing last bits of knowledge about msm_dsi_pll from dsi_manager. Signed-off-by:
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Dmitry Baryshkov authored
Use devm_of_clk_add_hw_provider() to register provided clocks. This allows dropping the remove function alltogether. Signed-off-by:
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Dmitry Baryshkov authored
Use devres-enabled version of clock registration functions. This lets us remove dsi_pll destroy callbacks completely. Signed-off-by:
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Dmitry Baryshkov authored
All MSM DSI PHYs provide two clocks: byte and pixel ones. Register/unregister provided clocks from the generic place, removing boilerplate code from all MSM DSI PHY drivers. Signed-off-by:
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Dmitry Baryshkov authored
msm_dsi_pll_set_usecase() function is not used outside of individual DSI PHY drivers, so drop it in favour of calling the the respective set_usecase functions directly. Signed-off-by:
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Dmitry Baryshkov authored
Signed-off-by:
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Dmitry Baryshkov authored
With the current upstream driver the msm_dsi_phy_type enum does not make much sense: all DSI PHYs are probed using the dt bindings, the phy type is not passed between drivers. Use quirks in phy individual PHY drivers to differentiate minor harware differences and drop the enum. Signed-off-by:
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Dmitry Baryshkov authored
Move all PLL-related callbacks into struct msm_dsi_phy_cfg. This limits the amount of data in the struct msm_dsi_pll. Signed-off-by:
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Dmitry Baryshkov authored
The only PLL using multiple enable sequences is the 28nm PLL, which just does the single step in the loop. Push that support back into the PLL code. Signed-off-by:
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