- 14 Jun, 2024 40 commits
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Leo Li authored
[Why] Compositors have different ways of assigning surfaces to DRM planes for render offloading. It may decide between various strategies: overlay, underlay, or a mix of both (see here for more info: https://gitlab.freedesktop.org/emersion/libliftoff/-/issues/76) One way for compositors to implement the underlay strategy is to assign a higher zpos to the DRM_PRIMARY plane than the DRM_OVERLAY planes, effectively turning the DRM_OVERLAY plane into an underlay plane. Today, amdgpu attaches an immutable zpos of 0 to the DRM_PRIMARY plane. This however, is an arbitrary restriction. DCN pipes are general purpose, and can be arranged in any z-order. To support compositors using this allocation scheme, we can set a non-zero immutable zpos for the PRIMARY, allowing the placement of OVERLAYS (mutable zpos range 0-254) beneath the PRIMARY. [How] Assign a zpos = #no of OVERLAY planes to the PRIMARY plane. Then, clean up any assumptions in the driver of PRIMARY plane having the lowest zpos. v2: Fix typo s/decending/descending/ Reviewed-by:
Harry Wentland <harry.wentland@amd.com> Acked-by:
Zaeem Mohamed <zaeem.mohamed@amd.com> Signed-off-by:
Leo Li <sunpeng.li@amd.com> Acked-by:
Pekka Paalanen <pekka.paalanen@collabora.com> Tested-by:
Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Leo Li authored
[Why] DCN is the display hardware for amdgpu. DRM planes are backed by DCN hardware pipes, which carry pixel data from one end (memory), to the other (output encoder). Each DCN pipe has the ability to blend in a cursor early on in the pipeline. In other words, there are no dedicated cursor planes in DCN, which makes cursor behavior somewhat unintuitive for compositors. For example, if the cursor is in RGB format, but the top-most DRM plane is in YUV format, DCN will not be able to blend them. Because of this, amdgpu_dm rejects all configurations where a cursor needs to be enabled on top of a YUV formatted plane. From a compositor's perspective, when computing an allocation for hardware plane offloading, this cursor-on-yuv configuration result in an atomic test failure. Since the failure reason is not obvious at all, compositors will likely fall back to full rendering, which is not ideal. Instead, amdgpu_dm can try to accommodate the cursor-on-yuv configuration by opportunistically reserving a separate DCN pipe just for the cursor. We can refer to this as "overlay cursor mode". It is contrasted with "native cursor mode", where the native DCN per-pipe cursor is used. [How] On each crtc, compute whether the cursor plane should be enabled in overlay mode. If it is, mark the CRTC as requesting overlay cursor mode. Overlay cursor should be enabled whenever there exists a underlying plane that has YUV format, or is scaled differently than the cursor. It should also be enabled if there is no underlying plane, or if underlying planes do not cover the entire CRTC. During DC validation, attempt to enable a separate DCN pipe for the cursor if it's in overlay mode. If that fails, or if no overlay mode is requested, then fallback to native mode. v2: * Update commit message for when overlay cursor should be enabled * Also consider scale and no-underlying-plane case (cursor on crtc bg) * Consider all underlying planes when determinig overlay/native, not just the plane immediately beneath the cursor, as it may not cover the entire CRTC. * Fix typo s/decending/descending/ * Force native cursor on pre-DCN hardware Reviewed-by:
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Josip Pavic authored
[Why & How] Define debug interface to dmub for reading back abm data. Reviewed-by:
Anthony Koo <anthony.koo@amd.com> Acked-by:
Josip Pavic <josip.pavic@amd.com> Tested-by:
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Wayne Lin authored
[Why] dm_dp_mst_is_port_support_mode() is a bit not following the original design rule and cause light up issue with multiple 4k monitors after mst dsc hub. [How] Refactor function dm_dp_mst_is_port_support_mode() a bit to solve the light up issue. Reviewed-by:
Jerry Zuo <jerry.zuo@amd.com> Acked-by:
Wayne Lin <wayne.lin@amd.com> Tested-by:
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Wayne Lin authored
[Why] When unplug one of monitors connected after mst hub, encounter null pointer dereference. It's due to dc_sink get released immediately in early_unregister() or detect_ctx(). When commit new state which directly referring to info stored in dc_sink will cause null pointer dereference. [how] Remove redundant checking condition. Relevant condition should already be covered by checking if dsc_aux is null or not. Also reset dsc_aux to NULL when the connector is disconnected. Reviewed-by:
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Paul Hsieh authored
[Why & How] Current DRAM setting would cause underflow on customer platform. Modify dram_clock_change_latency_us from 11.72 to 34.0 us as per recommendation from HW team Reviewed-by:
Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Acked-by:
Paul Hsieh <paul.hsieh@amd.com> Tested-by:
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Daniel Miess authored
[Why] Intermittent underflow observed when using 4k144 display on dcn351 [How] Update dram_clock_change_latency_us from 11.72us to 34us Reviewed-by:
Daniel Miess <daniel.miess@amd.com> Tested-by:
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Wayne Lin authored
[Why & How] It actually exposes '6' types in enum dmub_notification_type. Not 5. Using smaller number to create array dmub_callback & dmub_thread_offload has potential to access item out of array bound. Fix it. Reviewed-by:
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Wayne Lin authored
[Why & How] Link hpd status is set during link detection process via dpia_query_hpd_status(), doesn't need to explicitly set it during outbox irq. Remove it. Reviewed-by:
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Wayne Lin authored
[Why & How] Debug msg for usb4/tbt now is a bit confusing. Adjust it for better reading. Reviewed-by:
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Chris Park authored
[Why] Reference clock, either DPREFCLK or DTBCLK can be a value of 0 which then will encounter division by 0. [How] Avoid further calculation and programming if refclk is not populated. Reviewed-by:
Dillon Varone <dillon.varone@amd.com> Acked-by:
Chris Park <chris.park@amd.com> Tested-by:
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Joshua Aberback authored
[Why] DCN401 currently has an issue re-enabling when pipe splitting is enabled, while the root cause is being investigated we can make sure everything is being reset as a workaround, by disabling boot optimization. [How] - use enable_accelerated_mode instead of init_pipes to fully reset asic Reviewed-by:
Alvin Lee <alvin.lee2@amd.com> Acked-by:
Joshua Aberback <joshua.aberback@amd.com> Tested-by:
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Chris Park authored
[Why] uint32_t is implicitly converted to uint64_t while multiplication still happens on uint32_t side. This creates digit overflow for large pixel clock which is meant to be retained in uint64_t. [How] Calculate multiplication of units in uint64_t domain instead of uint32_t in DTO parameter clock caculation. Reviewed-by:
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Sridevi Arvindekar authored
Scaling and rotation changes for cursor. Reviewed-by:
Ariel Bernstein <eric.bernstein@amd.com> Reviewed-by:
Nevenko Stupar <nevenko.stupar@amd.com> Acked-by:
Sridevi Arvindekar <sarvinde@amd.com> Tested-by:
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Rodrigo Siqueira authored
Use the SPDX format for dmub_replay.c|.h files. Reviewed-by:
Aurabindo Pillai <aurabindo.pillai@amd.com> Acked-by:
Rodrigo Siqueira <rodrigo.siqueira@amd.com> Tested-by:
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Ivan Lipski authored
[WHY] The coverity analysis flagged this if expression as it contains a 'CONSTANT_EXPRESSION_RESULT': 'update_idle_uclk' is 'ORd' with itself. [HOW] Removed the duplicate 'update_idle_uclk'. Reviewed-by:
Alex Hung <alex.hung@amd.com> Acked-by:
Ivan Lipski <ivlipski@amd.com> Tested-by:
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George Shen authored
[Why] Passive DP40 cables were updated in the latest DP spec to support UHBR13.5 link rate. Current max link rate logic checks against the cable ID DPCD even for passive cables. [How] Ignore UHBR13.5 cable ID DPCD cap in get_max_link_rate logic. Reviewed-by:
Wenjing Liu <wenjing.liu@amd.com> Acked-by:
George Shen <george.shen@amd.com> Tested-by:
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Roman Li authored
[Why] replay_capability debugfs tells whether sink and driver support replay feature. However replay enablement also depends on whether it is enabled/disabled via amdgpu module params. [How] Add 'Config support' entry to output current replay config. Reviewed-by:
ChiaHsuan Chung <chiahsuan.chung@amd.com> Acked-by:
Roman Li <roman.li@amd.com> Tested-by:
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Yang Wang authored
refine gfx7 firmware loading Signed-off-by:
Yang Wang <kevinyang.wang@amd.com> Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
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winstang authored
[Why] prevent invalid memory access [How] check if dc and stream are NULL Co-authored-by:
winstang <winstang@amd.com> Reviewed-by:
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Jay Cornwall authored
In commit fda812eb ("drm/amdkfd: gfx12 context save/restore trap handler fixes") the following fix was introduced but incorrectly restricted to gfx12. The same issue and a corresponding fix apply to gfx10 and gfx11. Do not overwrite TRAPSTS.{SAVECTX,HOST_TRAP} when restoring this register. Both of these fields can assert while the wavefront is running the trap handler. Signed-off-by:
Jay Cornwall <jay.cornwall@amd.com> Reviewed-by:
Lancelot Six <lancelot.six@amd.com> Acked-by:
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Anthony Koo authored
- Change ordering of structs to put enums together - Add new define DMUB_TRACE_ENTRY_DEFINED to guard the trace code enum Acked-by:
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Nicholas Kazlauskas authored
[Why] Adds support for performing the sequential ONO changes from DCN351 into DCN35 ASIC based on revision. [How] Check the revision and run the DCN351 sequences on applicable revisions. Reviewed-by:
Sung joon Kim <sungjoon.kim@amd.com> Acked-by:
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Alvin Lee authored
[Description] Phantom DTBCLK can be calculated different from main because phantom has no DSC and thus will have a different output BPP. Ignore phantom DTBCLK requirement and only consider non-phantom DTBCLK requirements. Reviewed-by:
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Michael Strauss authored
[WHY] Some sinks are observed to return invalid LTTPR revision and/or invalid LTTPR link rate capabilities. [HOW] Assume any LTTPR which reports invalid max link rate supports HBR3. Don't validate LTTPR DPCD revision in dp_is_lttpr_present check. Reviewed-by:
Michael Strauss <michael.strauss@amd.com> Tested-by:
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Michael Strauss authored
[WHY] Needed for PHY patterns as well to perform electrical compliance. Also need to increase wait time from 30ms to 50ms to resolve very intermittent UHBR20 link training failures. Reviewed-by:
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Wenjing Liu authored
[why] We need to decrease ODM slice when adding or removing planes because MPO support takes precedence over dynamic ODM combine. However there is a case where we remove ODM combine even for ODM combine required timing in the initial new dc state. This is normally okay because ODM will be added back after we pass DML bandwidth validation. However since we remove ODM combine in the initial new state, the previous ODM pipe allocation is lost. This may cause the new plane to take away the original secondary OPP head pipe that is still required in the new state. For a timing that requires ODM 2:1 but optimized with ODM 4:1, if we add an MPO plane, we will not have enough pipe to preserve ODM 4:1. In this case we should reduce ODM slice count then try to add the MPO plane again. By reducing, we are gradually remove 1 ODM slice from right most side one at a time until we have enough free pipes for the new plane. If we remove ODM combine entirely, we could use the pipe at ODM slice index 1 as a DPP pipe for the new plane. But ODM slice 1 is still needed as the timing requires ODM 2:1. This transition is not seamless and user will see corruption on the screen. [how] Remove single ODM slice one at time until we have enough pipes for a new plane. Remove previous logic to always remove ODM combine entirely. Reviewed-by:
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Nevenko Stupar authored
[Why & How] Remove some cursor offset calculations for rotated cursor for fixing a bug where multiple cursors are seen. Reviewed-by:
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Daniel Sa authored
why: DML21 being overwritten after init. how: After initializing, early return. Reviewed-by:
Daniel Sa <daniel.sa@amd.com> Tested-by:
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Chris Park authored
[Why] Official Release CTA specification reverted the change and no longer uses version 5 to indicate OVT timing. [How] Change the version used for AVI info Frame for OVT to 4. Reviewed-by:
Leo Ma <hanghong.ma@amd.com> Acked-by:
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Alvin Lee authored
[Description] No need to assign stream_status NULL because it is always re-assigned before usage. This change is to fix coverity errors. Reviewed-by:
Nicholas Choi <nicholas.choi@amd.com> Acked-by:
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Zaeem Mohamed authored
[WHY] Duplicate headers requiring unecessary maintenance of both headers [HOW] Removal of smu13_driver_if header and all referneces to it changed to dcn32_smu13_driver Signed-off-by:
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Ivan Lipski authored
[WHY] Coverity analysis flagged this ternary operation as DEADCODE. Since 'total_y_free_entry' is initialized as 0x200 and 'total_c_free_entry' is initialized as 0x140, and they never change values before the ternary operator, so 'total_y_free_entry' is always greater 'total_c_free_entry', 'so small_free_entry' is always set to 'total_c_free_entry'. [HOW] Replace the ternary operator with the variable declaration. Signed-off-by:
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Ivan Lipski authored
[WHY] Coverity analysis flagged this code as DEADCODE since the condition and return in the outer loop are never reached. All operations with the 'dwb_pipe' variable happen in the inner loop, that already contains the same check with the 'MAX_DWB_PIPES'. The later check condition cannot occur before the check condition in the inner loop, thus the later condition is unreacable. [HOW] Remove the unreachable condition. Acked-by:
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Ivan Lipski authored
[WHY] Coverity analysis flagged the two if conditions in dcn30_dpp.c and dcn401_dpp.c as DEADCODE since they are never true, since the variable 'program_prealpha_dealpha' is initialized at 0 and never chagnes. [HOW] Removed the variable 'program_prealpha_dealpha' and the if conditions. Acked-by:
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Wenjing Liu authored
[why] OPP input rect aka odm slice rect is a hardware dependent parameter that can't be determined by SPL software logic. Therefore we need to explicitly pass odm slice rect in. So ODM slice rect calculation is moved out of SPL. [how] add odm_slice_rect parameter in spl_in Reviewed-by:
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Wenjing Liu authored
[why] When optc uses two pixel per container, each ODM slice width must be an even number. [how] If ODM slice width is odd number increase it by 1. Reviewed-by:
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Dennis Chan authored
When PHY power off, the DP_SEC_CNTL cannot be configured and cause disable Adaptive sync SDP failed. Regarding the issue, the driver will disabled AS-SDP in replay state machine. Reviewed-by:
Dennis Chan <dennis.chan@amd.com> Tested-by:
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ChunTao Tso authored
[Why] Because ABM will wait VStart to start getting histogram data, it will cause we can't enter IPS while full screnn video playing. [How] Modify the panel refresh rate to the maximun multiple of current refresh rate Reviewed-by:
ChunTao Tso <ChunTao.Tso@amd.com> Tested-by:
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Leon Huang authored
[Why] Dmub provides several Replay residency calculation methods, but current interface only supports either ALPM or PHY mode [How] Modify the interface for supporting different types of Replay residency calculation. Reviewed-by:
Leon Huang <Leon.Huang1@amd.com> Tested-by:
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