- 29 Jun, 2011 5 commits
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Becky Bruce authored
This has been broken for a while but hasn't been an issue until now because nobody was reserving regions at high addresses. Signed-off-by:
Becky Bruce <beckyb@kernel.crashing.org> Signed-off-by:
Benjamin Herrenschmidt <benh@kernel.crashing.org>
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Becky Bruce authored
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Scott Wood authored
On MMUs such as FSL where we can guarantee the entire linear mapping is bolted, we don't need to worry about linear TLB misses. If on top of that we do a full table walk, we get rid of all recursive TLB faults, and can dispense with some state saving. This gains a few percent on TLB-miss-heavy workloads, and around 50% on a benchmark that had a high rate of virtual page table faults under the normal handler. While touching the EX_TLB layout, remove EX_TLB_MMUCR0, EX_TLB_SRR0, and EX_TLB_SRR1 as they're not used. [BenH: Fixed build with 64K pages (wsp config)] Signed-off-by:
Scott Wood <scottwood@freescale.com> Signed-off-by:
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Scott Wood authored
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Benjamin Herrenschmidt authored
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- 28 Jun, 2011 2 commits
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Mike Williams authored
This will allow the new HW RNG driver to bind on these boards Signed-off-by:
Mike Williams <mike@mikebwilliams.com> Signed-off-by:
Josh Boyer <jwboyer@linux.vnet.ibm.com>
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Josh Boyer authored
The Sequoia board has a Security function IP block on it that contains a TRNG. Add the crypto and rng portions of that IP block to the DTS. Signed-off-by:
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- 27 Jun, 2011 19 commits
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Timur Tabi authored
The Freescale hypervisor does not allow guests to write to the timebase registers (virtualizing the timebase register was deemed too complicated), so don't try to synchronize the timebase registers when we're running under the hypervisor. This typically happens when kexec support is enabled. Signed-off-by:
Timur Tabi <timur@freescale.com> Signed-off-by:
Kumar Gala <galak@kernel.crashing.org>
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Prabhakar Kushwaha authored
P1010RDB Overview ----------------- 1Gbyte DDR3 (on board DDR) 32Mbyte 16bit NOR flash 32Mbyte SLC NAND Flash 256 Kbit M24256 I2C EEPROM 128 Mbit SPI Flash memory I2C Board 128x8 bit memory SD/MMC connector to interface with the SD memory card 2 SATA interface 1 internal SATA connect to 2.5. 160G SATA2 HDD 1 eSATA connector to rear panel USB 2.0 x1 USB 2.0 port: connected via a UTMI PHY to Mini-AB interface. x1 USB 2.0 port: directly connected to Mini-AB interface Ethernet eTSEC1: Connected to RGMII PHY VSC8641XKO eTSEC2: Connected to SGMII PHY VSC8221 eTSEC3: Connected to SGMII PHY VSC8221 eCAN Two DB-9 female connectors for Field bus interface UART DUART interface: supports two UARTs up to 115200 bps for console display Signed-off-by:Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by:
Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by:
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Timur Tabi authored
Enable framebuffer console support by default in the defconfig on the Freescale MPC8610 HPCD reference board. This allows the boot messages to be shown on the video display. Signed-off-by:
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Timur Tabi authored
mpc8610hpcd_set_pixel_clock() calculates the correct value of the PXCLK bits in the CLKDVDR register for a given pixel clock rate. The code which performs this calculation is overly complicated and includes an error estimation routine that doesn't work most of the time anyway. Replace the code with the simpler routine that's currently used on the P1022DS. Signed-off-by:
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Timur Tabi authored
Enable framebuffer console support by default in the defconfigs for the Freescale 85xx-based reference board. This allows the boot messages to be shown on the video display on the P1022DS. Signed-off-by:
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Timur Tabi authored
To ensure that the DIU pixel clock will not be set to an invalid value, clamp the PXCLK divider to the allowed range (2-255). This also acts as a limiter for the pixel clock. Signed-off-by:
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Scott Wood authored
e500mc cannot doze or nap due to an erratum (as well as having a different mechanism than previous e500), but it has a "wait" instruction that is similar to doze. On 64-bit, due to the soft-irq-disable mechanism, the existing book3e_idle should be used instead. Signed-off-by:
Vakul Garg <vakul@freescale.com> Signed-off-by:
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Kumar Gala authored
Split out common (non-board specific) parts of the SoC related device tree into a stub so multiple board dts files can include it and we can reduce duplication and maintenance effort. Signed-off-by: -
Baruch Siach authored
Cc: Kumar Gala <galak@kernel.crashing.org> Signed-off-by:
Baruch Siach <baruch@tkos.co.il> Signed-off-by:
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Timur Tabi authored
The platform file for the Freecale P1022DS reference board is not freeing the ioremap() mapping of the PIXIS and global utilities nodes it creates. Signed-off-by:
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Dmitry Eremin-Solenikov authored
fsl-lbc driver requires an interrupt to bind to localbus device. Populate 85xx boards' dts trees with lbc interrupt info. Signed-off-by:
Dmitry Eremin-Solenikov <dbaryshkov@gmail.com> Signed-off-by:
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Dmitry Eremin-Solenikov authored
Signed-off-by:
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Lei Xu authored
Signed-off-by:
Lei Xu <B33228@freescale.com> Signed-off-by:
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Lei Xu authored
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Prabhakar Kushwaha authored
FSL PCIe controller can act as agent(EP) or host(RC). Under Agent(EP) mode the controller will be configured by the host system. So its not required to be registered with the PCI(e) sub-system. We only register the controller if its configured in host(RC) mode. Signed-off-by:
Vivek Mahajan <vivek.mahajan@freescale.com> Signed-off-by:
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Timur Tabi authored
Add support for the ePAPR-compliant Freescale hypervisor (aka "Topaz") on the Freescale P3041DS, P4080DS, and P5020DS reference boards. Signed-off-by:
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Timur Tabi authored
Add functions to restart and halt the current partition when running under the Freescale hypervisor. These functions should be assigned to various function pointers of the ppc_md structure during the .probe() function for the board: ppc_md.restart = fsl_hv_restart; ppc_md.power_off = fsl_hv_halt; ppc_md.halt = fsl_hv_halt; Signed-off-by:
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Ashish Kalra authored
The Freescale ePAPR reference hypervisor provides interrupt controller services via a hypercall interface, instead of emulating the MPIC controller. This is called the VMPIC. The ePAPR "virtual interrupt controller" provides interrupt controller services for external interrupts. External interrupts received by a partition can come from two sources: - Hardware interrupts - hardware interrupts come from external interrupt lines or on-chip I/O devices. - Virtual interrupts - virtual interrupts are generated by the hypervisor as part of some hypervisor service or hypervisor-created virtual device. Both types of interrupts are processed using the same programming model and same set of hypercalls. Signed-off-by:Ashish Kalra <ashish.kalra@freescale.com> Signed-off-by:
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Timur Tabi authored
ePAPR hypervisors provide operating system services via a "hypercall" interface. The following steps need to be performed to make an hcall: 1. Load r11 with the hcall number 2. Load specific other registers with parameters 3. Issue instrucion "sc 1" 4. The return code is in r3 5. Other returned parameters are in other registers. To provide this service to the kernel, these steps are wrapped in inline assembly functions. Standard ePAPR hcalls are in epapr_hcalls.h, and Freescale extensions are in fsl_hcalls.h. Signed-off-by:
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- 23 Jun, 2011 14 commits
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Stuart Yoder authored
Move irq_choose_cpu() into arch/powerpc/kernel/irq.c so that it can be used by other PIC drivers. The function is not MPIC-specific. Signed-off-by:
Stuart Yoder <stuart.yoder@freescale.com> Signed-off-by:
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Kumar Gala authored
Only 32-bit SoCs have a QUICC Engine so limit the config option to PPC32. Signed-off-by: -
Kumar Gala authored
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Kumar Gala authored
We need the FSL specific header fixup code on both 32-bit and 64-bit platforms so just move the code into pci-common.c. Signed-off-by: -
Roy Zang authored
The P1023 processor is an e500v2 based SoC that utilizes the DPAA networking architecture. This adds basic board support for non-DPAA functionality (device tree, board file, etc). Signed-off-by:
Roy Zang <tie-fei.zang@freescale.com> Signed-off-by:
Haiying Wang <Haiying.Wang@freescale.com> Signed-off-by:
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Ashish Kalra authored
We expect this is actually faster, and we end up needing more space than we can get from the SPRGs in some instances. This is also useful when running as a guest OS - SPRGs4-7 do not have guest versions. 8 slots are allocated in thread_info for this even though we only actually use 4 of them - this allows space for future code to have more scratch space (and we know we'll need it for things like hugetlb). Signed-off-by:
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Scott Wood authored
In cases like when the platform is used under hypervisor we will NOT have an MPIC controller but still want doorbells setup. Signed-off-by:
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Kumar Gala authored
We fixup every FSL PCIe Root Complex we need to fixup a few things. Rather than adding every device under the sun we move to just matching only on the vendor (PCI_VENDOR_ID_FREESCALE) and than check that we are a PCIe controller in host mode in the fixup. Signed-off-by: -
Kumar Gala authored
Several changes on PCIe support on P3041DS/P4080DS/P5020DS boards: * Add support for "fsl,qoriq-pcie-v2.2" needed by P3041 & P5020 * Removed support for setting primary_phb_addr as we have no ISA need * Add PCI controller to of_platform_bus_probe (for EDAC) * Cleanup building w/SWIOTLB off on P4080DS (not stricly PCIe related) Signed-off-by:
Kai.Jiang <Kai.Jiang@freescale.com> Signed-off-by:
Laurentiu TUDOR <Laurentiu.Tudor@freescale.com> Signed-off-by:
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Kumar Gala authored
* Added BSD dual-license * Moved mpic-parent to root so we dont need to duplicate everywhere * Added next level cache from L2 to CPC * Moved to 4-cell MPIC interrupt properties * Added 3 MSI banks * Added numerous missing nodes: soc-sram-error, guts, pins, clockgen, rcpm, sfp, serdes, etc. * Reworked PCIe interrupts to be at virtual bridge level Signed-off-by: -
Kumar Gala authored
Add basic device tree for P3041DS board. This device tree excludes support for DPAA and RapidIO nodes. Signed-off-by: -
Kumar Gala authored
Add basic device tree for P5020DS board. This device tree excludes support for DPAA and RapidIO nodes. Signed-off-by: -
Kumar Gala authored
The e500mc and e5500 based cores are only available on corenet based SoCs. We use this name for the P204x, P3040, P4040, P4080, P50x0 SoCs and any future processors in these families. Signed-off-by: -
Kumar Gala authored
Rather than trying to use the core name we use corenet to distinquish the platform/core combo. corenet64 will be a 64-bit kernel build and we'll add a new defconfig for corenet32 for a 32-bit platforms. Signed-off-by:
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