- 13 Aug, 2024 1 commit
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Abhinav Kumar authored
sc7180 programs the ubwc settings as 0x1e as that would mean a highest bank bit of 14 which matches what the GPU sets as well. However, the highest_bank_bit field of the msm_mdss_data which is being used to program the SSPP's fetch configuration is programmed to a highest bank bit of 16 as 0x3 translates to 16 and not 14. Fix the highest bank bit field used for the SSPP to match the mdss and gpu settings. Fixes: 6f410b24 ("drm/msm/mdss: populate missing data") Reviewed-by:
Rob Clark <robdclark@gmail.com> Tested-by: Stephen Boyd <swboyd@chromium.org> # Trogdor.Lazor Patchwork: https://patchwork.freedesktop.org/patch/607625/ Link: https://lore.kernel.org/r/20240808235227.2701479-1-quic_abhinavk@quicinc.comSigned-off-by:
Abhinav Kumar <quic_abhinavk@quicinc.com>
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- 05 Aug, 2024 8 commits
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Dmitry Baryshkov authored
Take into account the plane rotation and flipping when calculating src positions for the wide plane parts. This is not an issue yet, because rotation is only supported for the UBWC planes and wide UBWC planes are rejected anyway because in parallel multirect case only the half of the usual width is supported for tiled formats. However it's better to fix this now rather than stumbling upon it later. Fixes: 80e8ae3b ("drm/msm/dpu: add support for wide planes") Reviewed-by:
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/601059/ Link: https://lore.kernel.org/r/20240627-dpu-virtual-wide-v5-3-5efb90cbb8be@linaro.orgSigned-off-by:
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Dmitry Baryshkov authored
YUV formats require only CSC to be enabled. Even decimated formats should not require scaler. Relax the requirement and don't check for the scaler block while checking if YUV format can be enabled. Fixes: 25fdd593 ("drm/msm: Add SDM845 DPU support") Signed-off-by:
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Dmitry Baryshkov authored
The QCM2290 doesn't have CSC blocks, so it can not support YUV formats even on ViG blocks. Fix the formats declared by _VIG_SBLK_NOSCALE(). Fixes: 5334087e ("drm/msm: add support for QCM2290 MDSS") Signed-off-by:
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Dmitry Baryshkov authored
If the dpu_format_populate_layout() fails, then FB is prepared, but not cleaned up. This ends up leaking the pin_count on the GEM object and causes a splat during DRM file closure: msm_obj->pin_count WARNING: CPU: 2 PID: 569 at drivers/gpu/drm/msm/msm_gem.c:121 update_lru_locked+0xc4/0xcc [...] Call trace: update_lru_locked+0xc4/0xcc put_pages+0xac/0x100 msm_gem_free_object+0x138/0x180 drm_gem_object_free+0x1c/0x30 drm_gem_object_handle_put_unlocked+0x108/0x10c drm_gem_object_release_handle+0x58/0x70 idr_for_each+0x68/0xec drm_gem_release+0x28/0x40 drm_file_free+0x174/0x234 drm_release+0xb0/0x160 __fput+0xc0/0x2c8 __fput_sync+0x50/0x5c __arm64_sys_close+0x38/0x7c invoke_syscall+0x48/0x118 el0_svc_common.constprop.0+0x40/0xe0 do_el0_svc+0x1c/0x28 el0_svc+0x4c/0x120 el0t_64_sync_handler+0x100/0x12c el0t_64_sync+0x190/0x194 irq event stamp: 129818 hardirqs last enabled at (129817): [<ffffa5f6d953fcc0>] console_unlock+0x118/0x124 hardirqs last disabled at (129818): [<ffffa5f6da7dcf04>] el1_dbg+0x24/0x8c softirqs last enabled at (129808): [<ffffa5f6d94afc18>] handle_softirqs+0x4c8/0x4e8 softirqs last disabled at (129785): [<ffffa5f6d94105e4>] __do_softirq+0x14/0x20 Fixes: 25fdd593 ("drm/msm: Add SDM845 DPU support") Signed-off-by:
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Abhinav Kumar authored
Before re-starting link training reset the link phy params namely the pre-emphasis and voltage swing levels otherwise the next link training begins at the previously cached levels which can result in link training failures. Fixes: 8ede2ecc ("drm/msm/dp: Add DP compliance tests on Snapdragon Chipsets") Reviewed-by:
Stephen Boyd <swboyd@chromium.org> Patchwork: https://patchwork.freedesktop.org/patch/605946/ Link: https://lore.kernel.org/r/20240725220450.131245-1-quic_abhinavk@quicinc.comSigned-off-by:
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Abhinav Kumar authored
For cases where the crtc's connectors_changed was set without enable/active getting toggled , there is an atomic_enable() call followed by an atomic_disable() but without an atomic_mode_set(). This results in a NULL ptr access for the dpu_encoder_get_drm_fmt() call in the atomic_enable() as the dpu_encoder's connector was cleared in the atomic_disable() but not re-assigned as there was no atomic_mode_set() call. Fix the NULL ptr access by moving the assignment for atomic_enable() and also use drm_atomic_get_new_connector_for_encoder() to get the connector from the atomic_state. Fixes: 25fdd593 ("drm/msm: Add SDM845 DPU support") Reported-by:
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Abhinav Kumar authored
Fix the dp_panel_get_supported_bpp() API to return the minimum supported bpp correctly for relevant cases and use this API to correct the behavior of DP driver which hard-codes the max supported bpp to 30. This is incorrect because the number of lanes and max data rate supported by the lanes need to be taken into account. Replace the hardcoded limit with the appropriate math which accounts for the accurate number of lanes and max data rate. changes in v2: - Fix the dp_panel_get_supported_bpp() and use it - Drop the max_t usage as dp_panel_get_supported_bpp() already returns the min_bpp correctly now changes in v3: - replace min_t with just min as all params are u32 Fixes: c943b494 ("drm/msm/dp: add displayPort driver support") Reported-by:
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Dmitry Baryshkov authored
DPU debugging macros need to be converted to a proper drm_debug_* macros, however this is a going an intrusive patch, not suitable for a fix. Wire DPU_DEBUG and DPU_DEBUG_DRIVER to always use DRM_DEBUG_DRIVER to make sure that DPU debugging messages always end up in the drm debug messages and are controlled via the usual drm.debug mask. I don't think that it is a good idea for a generic DPU_DEBUG macro to be tied to DRM_UT_KMS. It is used to report a debug message from driver, so by default it should go to the DRM_UT_DRIVER channel. While refactoring debug macros later on we might end up with particular messages going to ATOMIC or KMS, but DRIVER should be the default. Fixes: 25fdd593 ("drm/msm: Add SDM845 DPU support") Signed-off-by:
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- 03 Jul, 2024 1 commit
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Danila Tikhonov authored
Add the DSI host found on SM7150. Signed-off-by:
Danila Tikhonov <danila@jiaxyga.com> Reviewed-by:
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/601231/Signed-off-by:
Rob Clark <robdclark@chromium.org>
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- 02 Jul, 2024 2 commits
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Rob Clark authored
Fixes a sparse "different address spaces" error. Reported-by:
kernel test robot <lkp@intel.com> Closes: https://lore.kernel.org/oe-kbuild-all/202406280050.syeEwLTE-lkp@intel.com/Signed-off-by:
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Rob Clark authored
The __build_asserts() function only exists to have a place to put build-time asserts. Reported-by:
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- 01 Jul, 2024 2 commits
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Daniil Titov authored
This GPU is found on SoCs such as MSM8937 (450 MHz), MSM8940 (475 MHz), SDM439 (650 MHz). Signed-off-by:
Daniil Titov <daniilt971@gmail.com> Reviewed-by:
Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by:
Barnabás Czémán <trabarni@gmail.com> Patchwork: https://patchwork.freedesktop.org/patch/601411/Signed-off-by:
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Abhinav Kumar authored
On QCM2290 chipset DPU does not support UBWC. Add a dpu cap to indicate this and do not expose compressed formats in this case. changes since RFC: - use ubwc enc and dec version of mdss_data instead of catalog to decide if ubwc is supported Signed-off-by:
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- 29 Jun, 2024 7 commits
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Akhil P Oommen authored
To simplify, introduce the new gmu_chipid for a740 & a750 GPUs. Signed-off-by:
Akhil P Oommen <quic_akhilpo@quicinc.com> Reviewed-by:
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Akhil P Oommen authored
Add support in drm/msm driver for the Adreno X185 gpu found in Snapdragon X1 Elite chipset. Signed-off-by:
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Akhil P Oommen authored
Document Adreno X185 GMU in the dt-binding specification. Signed-off-by:
Krzysztof Kozlowski <krzk@kernel.org> Patchwork: https://patchwork.freedesktop.org/patch/601395/Signed-off-by:
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Neil Armstrong authored
Disable the call to qcom_scm_gpu_init_regs() for a730 and a740 after init failures on the HDK8550 and HDK8450 platforms: msm_dpu ae01000.display-controller: failed to load adreno gpu msm_dpu ae01000.display-controller: failed to bind 3d00000.gpu (ops a3xx_ops [msm]): -5 msm_dpu ae01000.display-controller: adev bind failed: -5 While debugging, it happens the call to: qcom_scm_gpu_init_regs(QCOM_SCM_GPU_ALWAYS_EN_REQ) returns -5 and makes the gpu fail to initialize. Remove the scm call since it's not done downstream either and works fine without. Fixes: 14b27d5d ("drm/msm/a7xx: Initialize a750 "software fuse"") Signed-off-by:
Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by:
Connor Abbott <cwabbott0@gmail.com> Patchwork: https://patchwork.freedesktop.org/patch/600972/Signed-off-by:
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Neil Armstrong authored
The gpulist has twice the a6xx gpulist, replace the second one with the a7xx gpulist. Solves: msm_dpu ae01000.display-controller: Unknown GPU revision: 7.3.0.1 msm_dpu ae01000.display-controller: Unknown GPU revision: 67.5.10.1 msm_dpu ae01000.display-controller: Unknown GPU revision: 67.5.20.1 on SM8450, SM8550 & SM8560. Fixes: 8ed322f6 ("drm/msm/adreno: Split up giant device table") Signed-off-by:
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Konrad Dybcio authored
Commit f6ebff4fe810 ("drm/msm/adreno: De-spaghettify the use of memory barriers") made some fixups relating to write arrival, ensuring that the GPU's memory interface has *really really really* been told to come out of reset. That in turn rendered the hacky commit being reverted no longer necessary. Get rid of it. This reverts commit b7753280 ("drm/msm/a6xx: Poll for GBIF unhalt status in hw_init") Signed-off-by: -
Konrad Dybcio authored
Memory barriers help ensure instruction ordering, NOT time and order of actual write arrival at other observers (e.g. memory-mapped IP). On architectures employing weak memory ordering, the latter can be a giant pain point, and it has been as part of this driver. Moreover, the gpu_/gmu_ accessors already use non-relaxed versions of readl/writel, which include r/w (respectively) barriers. Replace the barriers with a readback (or drop altogether where possible) that ensures the previous writes have exited the write buffer (as the CPU must flush the write to the register it's trying to read back). Signed-off-by:
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- 25 Jun, 2024 6 commits
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Rob Clark authored
Merge remote-tracking branch 'qcom/20240430-a750-raytracing-v3-2-7f57c5ac082d@gmail.com' into msm-next-robclark Merge qcom drivers to pick up dependency for SMEM based speedbin. Signed-off-by: -
Krzysztof Kozlowski authored
dtschema v2024.4, v2024.5 and maybe earlier do not select device nodes for given binding validation if the schema contains compatible list with pattern and a const fallback. This leads to binding being a no-op - not being applied at all. Issue should be fixed in the dtschema but for now add a work-around do the binding can be used against DTS validation. Signed-off-by:
Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20240623-qcom-adreno-dts-bindings-driver-v2-4-9496410de992@linaro.orgSigned-off-by:
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Krzysztof Kozlowski authored
Regex for newer Adreno compatibles can be simpler. Suggested-by:
Conor Dooley <conor@kernel.org> Signed-off-by:
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Krzysztof Kozlowski authored
All devices should (and actually do) have same order of entries, if possible. That's the case for reg/reg-names, so define the reg-names in top-level to enforce that. Acked-by:
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Krzysztof Kozlowski authored
We expect each schema with variable number of clocks, to have the widest constrains in top-level "properties:". This is more readable and also makes binding stricter, if there is no "if:then:" block for given variant. Acked-by:
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Dmitry Baryshkov authored
The frame event callback is always set to dpu_crtc_frame_event_cb() (or to NULL) and the data is always either the CRTC itself or NULL (correpondingly). Thus drop the event callback registration, call the dpu_crtc_frame_event_cb() directly and gate on the dpu_enc->crtc assigned using dpu_encoder_assign_crtc(). Signed-off-by:
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- 24 Jun, 2024 13 commits
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Daniil Titov authored
Add phy configuration for 28nm dsi phy found on MSM8937 SoC. Only difference from existing msm8916 configuration is number of phy and io_start addresses. Signed-off-by:
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Barnabás Czémán authored
The MSM8937 SoC uses a slightly different 28nm dsi phy. Add a new compatible for it. Reviewed-by:
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Daniil Titov authored
Add the mdp5_cfg_hw entry for MDP5 version v1.14 found on msm8937. Signed-off-by:
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Barnabás Czémán authored
Add the compatible for the MDP5 found on MSM8937. Reviewed-by:
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Barnabás Czémán authored
Remove MDP_CAP_SRC_SPLIT from msm8x53_config because it is not referenced in downstream. Fixes: fb25d447 ("drm/msm/mdp5: Add configuration for MDP v1.16") Signed-off-by:
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Jani Nikula authored
Prefer the struct drm_edid based functions for reading the EDID and updating the connector. Simplify the flow by updating the EDID property when the EDID is read instead of at .get_modes. Signed-off-by:
Jani Nikula <jani.nikula@intel.com> Reviewed-by:
Douglas Anderson <dianders@chromium.org> Patchwork: https://patchwork.freedesktop.org/patch/593976/ Link: https://lore.kernel.org/r/93d6c446ed4831dadfb4a77635a67cf5f27e19ff.1715691257.git.jani.nikula@intel.comSigned-off-by:
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Barnabás Czémán authored
CTLs on older qualcomm SOCs like msm8953 and msm8996 has not got interrupts, so better to skip CTL irq callback register/unregister make dpu_ctl_cfg be able to define without intr_start. Signed-off-by:
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Dmitry Baryshkov authored
Rename dpu_hw_setup_vsync_source functions to make the names match the implementation: on DPU 5.x the TOP only contains timer setup, while 3.x and 4.x used MDP_VSYNC_SEL register to select TE source. Signed-off-by:
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Dmitry Baryshkov authored
Make the DPU driver use the TE source specified in the DT. If none is specified, the driver defaults to the first GPIO (mdp_vsync_p). Signed-off-by:
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Dmitry Baryshkov authored
Allow board's device tree to specify the vsync source (aka TE source). If the property is omitted, the display controller driver will use the default setting. Reviewed-by:
Marijn Suijten <marijn.suijten@somainline.org> Patchwork: https://patchwork.freedesktop.org/patch/598740/ Link: https://lore.kernel.org/r/20240613-dpu-handle-te-signal-v2-6-67a0116b5366@linaro.org
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Dmitry Baryshkov authored
The struct msm_display_info has is_te_using_watchdog_timer field which is neither set anywhere nor is flexible enough to specify different sources. Replace it with the field specifying the vsync source using enum dpu_vsync_source. Reviewed-by:
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Dmitry Baryshkov authored
Setting vsync source makes sense only for DSI CMD panels. Pull the is_cmd_mode condition out of the function into the calling code, so that it becomes more explicit. Reviewed-by:
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Dmitry Baryshkov authored
Neither disp-enable-gpios nor disp-te-gpios are defined in the schema. None of the board DT files use those GPIO pins. Drop them from the driver. Reviewed-by:
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