- 26 May, 2023 38 commits
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Krzysztof Kozlowski authored
Re-order the clocks for MMCC clock controller node to match the bindings (Linux driver takes by name): msm8996-mtp.dtb: clock-controller@8c0000: clock-names:1: 'gpll0' was expected msm8996-mtp.dtb: clock-controller@8c0000: clock-names:2: 'gcc_mmss_noc_cfg_ahb_clk' was expected Signed-off-by:
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by:
Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by:
Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230507174516.264936-2-krzysztof.kozlowski@linaro.org
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Krzysztof Kozlowski authored
Re-order the clocks for LPASS CPU node to match the bindings (Linux driver takes by name): msm8916-asus-z00l.dtb: audio-controller@7708000: clock-names:1: 'mi2s-bit-clk0' was expected msm8916-asus-z00l.dtb: audio-controller@7708000: clock-names:2: 'mi2s-bit-clk1' was expected msm8916-asus-z00l.dtb: audio-controller@7708000: clock-names:3: 'mi2s-bit-clk2' was expected msm8916-asus-z00l.dtb: audio-controller@7708000: clock-names:4: 'mi2s-bit-clk3' was expected msm8916-asus-z00l.dtb: audio-controller@7708000: clock-names:5: 'pcnoc-mport-clk' was expected msm8916-asus-z00l.dtb: audio-controller@7708000: clock-names:6: 'pcnoc-sway-clk' was expected Signed-off-by:
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Vijaya Krishna Nivarthi authored
As part of DMA mode support to qspi driver. Signed-off-by:
Vijaya Krishna Nivarthi <quic_vnivarth@quicinc.com> Reviewed-by:
Douglas Anderson <dianders@chromium.org> Signed-off-by:
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Vijaya Krishna Nivarthi authored
As part of DMA mode support to qspi driver. Signed-off-by:
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Vijaya Krishna Nivarthi authored
As part of DMA mode support to qspi driver. Signed-off-by:
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Krzysztof Kozlowski authored
The bus@0 node should have reg or ranges to fix dtbs W=1 warnings: Warning (unit_address_vs_reg): /soc@0/bus@0: node has a unit name, but no reg or ranges property Warning (simple_bus_reg): /soc@0/bus@0: missing or empty reg/ranges property Signed-off-by:
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Krzysztof Kozlowski authored
SoC DTSI already comes with 85800000 reserved memory node, so assume the author wanted to update its length. This fixes dtbs W=1 warning: Warning (unique_unit_address_if_enabled): /reserved-memory/qhee-code@85800000: duplicate unit-address (also used in node /reserved-memory/reserved@85800000) Signed-off-by:
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Krzysztof Kozlowski authored
Bindings expect ADC channel node names to follow specific pattern: sm6125-xiaomi-laurel-sprout.dtb: adc@3100: 'adc-chan@4d', 'adc-chan@4e', 'adc-chan@52', 'adc-chan@54' do not match any of the regexes: ... Signed-off-by:
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Krzysztof Kozlowski authored
The SM8550 DTSI defines a fixed PCIE1 PHY AUX clock and expects boards to define frequency. Use the same as in MTP8550 to fix: sm8550-qrd.dtb: pcie-1-phy-aux-clk: 'clock-frequency' is a required property Signed-off-by:
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Krzysztof Kozlowski authored
Since commit 6c84bbd1 ("dt-bindings: arm-smmu: Add generic qcom,smmu-500 bindings") the SMMU is supposed to use qcom,smmu-500 compatible fallback: ['qcom,sm8250-smmu-500', 'qcom,adreno-smmu', 'qcom,smmu-500', 'arm,mmu-500'] is too long 'qcom,sm8250-smmu-500' is not one of ['qcom,msm8996-smmu-v2', 'qcom,msm8998-smmu-v2', 'qcom,sdm630-smmu-v2'] 'qcom,sm8250-smmu-500' is not one of ['qcom,msm8996-smmu-v2', 'qcom,sc7180-smmu-v2', 'qcom,sdm630-smmu-v2', 'qcom,sdm845-smmu-v2' Signed-off-by:
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Krzysztof Kozlowski authored
Since commit 6c84bbd1 ("dt-bindings: arm-smmu: Add generic qcom,smmu-500 bindings") the SMMU is supposed to use qcom,smmu-500 compatible fallback: ['qcom,qdu1000-smmu-500', 'arm,mmu-500'] is too short ['qcom,qdu1000-smmu-500', 'arm,mmu-500'] is too long Signed-off-by:
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Krzysztof Kozlowski authored
The spi-max-frequency property belongs to SPI devices, not SPI controller: ipq8074-hk01.dtb: spi@78b5000: Unevaluated properties are not allowed ('spi-max-frequency' was unexpected) Signed-off-by: -
Krzysztof Kozlowski authored
The spi-max-frequency property belongs to SPI devices, not SPI controller: ipq6018-cp01-c1.dtb: spi@78b5000: Unevaluated properties are not allowed ('spi-max-frequency' was unexpected) Signed-off-by: -
Vignesh Viswanathan authored
In IPQ SoCs, bootloader will collect the system RAM contents upon crash for the post morterm analysis. If we don't reserve the memory region used by bootloader, obviously linux will consume it and upon next boot on crash, bootloader will be loaded in the same region, which will lead to loose some of the data, sometimes we may miss out critical information. So lets reserve the region used by the bootloader. Similarly SBL copies some data into the reserved region and it will be used in the crash scenario. So reserve 1MB for SBL as well. While at it, drop the size padding in the reserved memory region, wherever applicable. Signed-off-by:
Vignesh Viswanathan <quic_viswanat@quicinc.com> Signed-off-by:
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Vignesh Viswanathan authored
Like any other Qualcomm SoCs, IPQ8074 and IPQ6018 also supports the download mode to collect the RAM dumps if system crashes, to perform the post mortem analysis. Add support for the same. Signed-off-by:
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Neil Armstrong authored
Add crypto engine (CE) and CE BAM related nodes and definitions for the SM8450 SoC. Tested-by:
Anders Roxell <anders.roxell@linaro.org> Tested-by:
Linux Kernel Functional Testing <lkft@linaro.org> Signed-off-by:
Neil Armstrong <neil.armstrong@linaro.org> [Bhupesh: Corrected the compatible list] Signed-off-by:
Bhupesh Sharma <bhupesh.sharma@linaro.org> Signed-off-by:
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Bhupesh Sharma authored
Add crypto engine (CE) and CE BAM related nodes and definitions to 'sm8350.dtsi'. Co-developed-by and Signed-off-by: Robert Foss <rfoss@kernel.org> [Bhupesh: Switch to '#interconnect-cells = <2>', available since commit 4f287e31] Tested-by:
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Bhupesh Sharma authored
Add crypto engine (CE) and CE BAM related nodes and definitions to 'sm8250.dtsi'. Co-developed-by and Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org> Tested-by:
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Bhupesh Sharma authored
Add crypto engine (CE) and CE BAM related nodes and definitions to 'sm8150.dtsi'. Tested-by:
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Bhupesh Sharma authored
Add crypto engine (CE) and CE BAM related nodes and definitions to 'sm6115.dtsi'. Reviewed-by:
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Bhupesh Sharma authored
As per documentation, Qualcomm SDM845 SoC supports SLIMBAM DMA engine v1.7.4, so use the correct compatible strings. Reviewed-by:
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Bhupesh Sharma authored
As per documentation, Qualcomm SM8550 SoC supports BAM DMA engine v1.7.4, so use the correct compatible strings. Reviewed-by:
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Kathiravan T authored
IPQ9574 has efuse region to determine the various HW quirks. Lets add the initial support and the individual fuses will be added as they are required. Reviewed-by:
Kathiravan T <quic_kathirav@quicinc.com> Signed-off-by:
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Kathiravan T authored
IPQ6018 has efuse region to determine the various HW quirks. Lets add the initial support and the individual fuses will be added as they are required. Signed-off-by:
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by:
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Kathiravan T authored
IPQ5332 has efuse region to determine the various HW quirks. Lets add the initial support and the individual fuses will be added as they are required. Reviewed-by:
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Kathiravan T authored
Add the QFPROM compatible for IPQ5332, IPQ6018 and IPQ9574 Signed-off-by:
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Devi Priya authored
Add the initial device tree support for the Reference Design Platform (RDP) 453 based on IPQ9574 family of SoCs. This patch adds support for Console UART, SPI NOR and SMPA1 regulator node. Signed-off-by:
Devi Priya <quic_devipriy@quicinc.com> Signed-off-by:
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Devi Priya authored
Document AL02-C8 (Reference Design Platform 453) board based on IPQ9574 family of SoCs. Signed-off-by:
Conor Dooley <conor.dooley@microchip.com> Signed-off-by:
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Devi Priya authored
Add the initial device tree support for the Reference Design Platform (RDP) 449 based on IPQ9574 family of SoCs. This patch adds support for Console UART, SPI NOR and SMPA1 regulator node. Signed-off-by:
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Devi Priya authored
Document AL02-C6 (Reference Design Platform 449) board based on IPQ9574 family of SoCs. Signed-off-by:
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Devi Priya authored
Add the initial device tree support for the Reference Design Platform (RDP) 418 based on IPQ9574 family of SoCs. This patch adds support for Console UART, SPI NOR, eMMC and SMPA1 regulator node. Co-developed-by:
Anusha Rao <quic_anusha@quicinc.com> Signed-off-by:
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Devi Priya authored
Document AL02-C2 (Reference Design Platform 418) board based on IPQ9574 family of SoCs. Signed-off-by:
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Devi Priya authored
Add cpu freq nodes in the device tree to bump cpu frequency above 800MHz. Reviewed-by:
Praveenkumar I <quic_ipkumar@quicinc.com> Signed-off-by:
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Devi Priya authored
Add support for SMPA1 regulator node in IPQ9574. Reviewed-by:
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Devi Priya authored
Add RPM Glink & RPM message RAM nodes to support frequency scaling on IPQ9574. Reviewed-by:
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Devi Priya authored
Add the APCS & A73 PLL nodes to support CPU frequency scaling. Signed-off-by:
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Devi Priya authored
Rename the dts after Reference Design Platform(RDP) to adopt standard naming convention. Acked-by:
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Luca Weiss authored
This file is using definitions from the spmi-vadc header, so we need to include it. Fixes: 11975b9b ("arm64: dts: qcom: Add pm7250b PMIC") Signed-off-by:
Luca Weiss <luca.weiss@fairphone.com> Signed-off-by:
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- 25 May, 2023 2 commits
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Bryan O'Donoghue authored
Add a basic booting DTS for the Sony Xperia M4 Aqua aka "tulip". Tulip is paired with: - wcn3660 - smb1360 battery charger - 720p Truly NT35521 Panel Reviewed-by:
Bryan O'Donoghue <bryan.odonoghue@linaro.org> Signed-off-by:
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Bryan O'Donoghue authored
The apq8039-t2 is an apq8039 based board paired with a wcn3680b WiFi chipset. Co-developed-by:
Shawn Guo <shawn.guo@linaro.org> Signed-off-by:
Jun Nie <jun.nie@linaro.org> Signed-off-by:
Benjamin Li <benl@squareup.com> Signed-off-by:
James Willcox <jwillcox@squareup.com> Signed-off-by:
Leo Yan <leo.yan@linaro.org> Signed-off-by:
Joseph Gates <jgates@squareup.com> Signed-off-by:
Max Chen <mchen@squareup.com> Signed-off-by:
Zac Crosby <zac@squareup.com> Signed-off-by:
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