- 18 May, 2018 39 commits
-
-
Xingyue Tao authored
- Adds int max_downscale_src_width in dc struct - Checks and does not support if downscale size is more than 4k (width > 3840) Signed-off-by:
Xingyue Tao <xingyue.tao@amd.com> Reviewed-by:
Charlene Liu <Charlene.Liu@amd.com> Acked-by:
Harry Wentland <harry.wentland@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
-
Dmytro Laktyushkin authored
Signed-off-by:
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by:
Tony Cheng <Tony.Cheng@amd.com> Acked-by:
-
Dmytro Laktyushkin authored
Signed-off-by:
Eric Yang <eric.yang2@amd.com> Acked-by:
-
Eric Bernstein authored
Signed-off-by:
Eric Bernstein <eric.bernstein@amd.com> Reviewed-by:
-
Charlene Liu authored
[Description] for any reason, if driver detects HUBP underflow, if a debug option enabled to enable recovery. it will kick in a sequence of recovery. Signed-off-by:
-
Dmytro Laktyushkin authored
Signed-off-by:
-
Dmytro Laktyushkin authored
Signed-off-by:
-
Anthony Koo authored
Remove dependency on the old FREESYNC_SW_STATS log mask used by DAL2 Also rename from profiling to displaystats Signed-off-by:
Anthony Koo <Anthony.Koo@amd.com> Reviewed-by:
Aric Cyr <Aric.Cyr@amd.com> Acked-by:
-
Dmytro Laktyushkin authored
Signed-off-by:
-
Dmytro Laktyushkin authored
32.32 is redundant, 31.32 does everything we use 32.32 for Signed-off-by:
-
Anthony Koo authored
Signed-off-by:
-
Alex Deucher authored
Take the encode rings into account in the idle work handler. Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
-
Alex Deucher authored
Take the encode rings into account in the idle work handler. v2: fix typo: s/num_uvd_inst/num_enc_rings/ Reviewed-by:
James Zhu <James.Zhu@amd.com> Reviewed-by:
-
Alex Deucher authored
Current multi-UVD hardware uses a single clock and power source so handle all instances in the idle handler. Reviewed-by:
-
Nayan Deshmukh authored
That got missed while moving the files outside of amdgpu. Signed-off-by:
Nayan Deshmukh <nayan26deshmukh@gmail.com> Reviewed-by:
-
Tom St Denis authored
NFC just comments. (v2): Updated based on feedback from Alex Deucher. Signed-off-by:
Tom St Denis <tom.stdenis@amd.com> Reviewed-by:
-
Dan Carpenter authored
We added some more lines of code to this if statement but forgot to add curly braces. Fixes: 0c24e7ef ("drm/amd/powerplay: add specific changes for VEGAM in smu7_hwmgr.c") Signed-off-by:
Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by:
-
Alex Deucher authored
- Remove unused ASICREV_IS_VEGA12_p() macro - Fix ASICREV_IS_VEGA12_P() macro to properly check against vega20 Reviewed-by:
-
Alex Deucher authored
Leftover from bringup. No need to keep it around for upstream. Reviewed-by:
-
Alex Deucher authored
Leftover from bringup. No need to keep it around for upstream. Reviewed-by:
Michel Dänzer <michel.daenzer@amd.com> Signed-off-by:
-
Andrey Grodzovsky authored
This spinlock is superfluous, any call to drm_sched_entity_push_job should already be under a lock together with matching drm_sched_job_init to match the order of insertion into queue with job's fence seqence number. v2: Improve patch description. Add functions documentation describing the locking considerations Signed-off-by:
Andrey Grodzovsky <andrey.grodzovsky@amd.com> Acked-by:
Chunming Zhou <david1.zhou@amd.com> Reviewed-by:
-
Christian König authored
This lock isn't used any more. Signed-off-by:
-
Rex Zhu authored
Screen flickering observed while running 1080p video using MPV_VAAPI/VDPAU with 4x4K@60 monitors Need to set higher mclk in this configuration. Reviewed-by:
Rex Zhu <Rex.Zhu@amd.com> Signed-off-by:
-
Andrey Grodzovsky authored
Following change 75fbed20 we never initialize or use the GPU scheduler for KIQ and hence we need to skip KIQ ring when iterating amdgpu_ctx's scheduler entites. Signed-off-by:
-
Alex Deucher authored
Must set amdgpu.exp_hw_support=1 on the kernel command line in grub to enable support. Reviewed-by:
-
Feifei Xu authored
Acked-by:
Feifei Xu <Feifei.Xu@amd.com> Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
-
Feifei Xu authored
v2: fix whitespace (Alex) Reviewed-by:
Huang Rui <ray.huang@amd.com> Signed-off-by:
-
Feifei Xu authored
New df helpers for 3.6. v2: switch to using df 3.6 headers (Alex) Acked-by:
-
Alex Deucher authored
Needed for vega20. Acked-by:
-
James Zhu authored
Vega20 ucode load type is set to AMDGPU_FW_LOAD_DIRECT for default. So UVD/VCE needn't PSP IP block up. UVD/VCE for Vega20 can be enabled at this moment. Signed-off-by:
Leo Liu <leo.liu@amd.com> Signed-off-by:
-
James Zhu authored
Enable 2nd instance uvd queue maping for uvd 7.2. For user, only one UVD instance presents. there is two rings for uvd decode, and 4 rings for uvd encode. Signed-off-by:
-
James Zhu authored
For Vega20, the 2nd instance uvd IRQ using different client id. Enable the 2nd instance IRQ for uvd 7.2 Signed-off-by:
-
James Zhu authored
For Vega20, there are two UVD hardware. Need add the 2nd IH client ID for the 2nd UVD Hardware. Signed-off-by:
-
James Zhu authored
For Vega20, set num of uvd instance to 2, to enble 2nd instance. The IB test build-in registers need update for vega20 2nd instance. Signed-off-by:
-
James Zhu authored
For Vega20, there are two UVD Hardware. One more UVD hardware adds one decode ring and two encode rings. So AMDGPU_MAX_RINGS need increase by 3. Signed-off-by:
-
James Zhu authored
Vega20 has dual-UVD. Need add multiple instances support for uvd. Restruct uvd.inst, using uvd.inst[0] to replace uvd.inst->. Repurpose amdgpu_ring::me for instance index, and initialize to 0. There are no any logical changes here. Signed-off-by:
-
James Zhu authored
Vega20 has dual-UVD. Need Restruct amdgpu_device::uvd to support multiple uvds. There are no any logical changes here. Signed-off-by:
-
Feifei Xu authored
Please enable above ips on soc15.c when they're available. Reviewed-by:
-
Evan Quan authored
v2: remove duplicate flag. Reviewed-by:
Evan Quan <evan.quan@amd.com> Reviewed-by:
-
- 17 May, 2018 1 commit
-
-
Feifei Xu authored
Please revert this patch when psp load fw is enabled. Acked-by:
-
