- 26 Oct, 2023 40 commits
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Lijo Lazar authored
Issue a read to confirm the register write before ringing doorbell. With multiple XCCs there is chance for race condition. Signed-off-by:
Lijo Lazar <lijo.lazar@amd.com> Acked-by:
Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by:
Asad Kamal <asad.kamal@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Yifan Zhang authored
is_mode1_reset_supported may be called before smu init, when smu_context is unitialized in driver load/unload test. Call smu_cmn_get_smc_version explicitly in is_mode1_reset_supported. v2: apply to aldebaran in case is_mode1_reset_supported will be uncommented (Candice Li) Fixes: 710d9cae ("drm/amd/pm: drop most smu_cmn_get_smc_version in smu") Signed-off-by:
Yifan Zhang <yifan1.zhang@amd.com> Reviewed-by:
Candice Li <candice.li@amd.com> Acked-by:
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Tao Zhou authored
Add DF block and RAS poison mode query for DF v4_6_2. Signed-off-by:
Tao Zhou <tao.zhou1@amd.com> Reviewed-by:
Stanley.Yang <Stanley.Yang@amd.com> Acked-by:
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Lijo Lazar authored
Use subrevision of IP version in discovery table to identify SOC revision id for NBIO v7.9 SOCs. Only newer bootloaders update subrevision field. Signed-off-by:
Le Ma <le.ma@amd.com> Signed-off-by:
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Aric Cyr authored
DC v3.2.256 Summary: * Fixes null-deref regression after "drm/amd/display: Update OPP counter from new interface" * Fixes display flashing when VSR and HDR enabled on dcn32 * Fixes dcn3x intermittent hangs due to FPO * Fixes MST Multi-Stream light up on dcn35 * Fixes green screen on DCN31x when DVI and HDMI monitors attached * Adds DML2 improvements * Adds idle power optimization improvements * Accommodates panels with lower nit backlight * Updates SDP VSC colorimetry from DP test automation request * Reverts "drm/amd/display: allow edp updates for virtual signal" Acked-by:
Roman Li <roman.li@amd.com> Signed-off-by:
Aric Cyr <aric.cyr@amd.com> Tested-by:
Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by:
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Aurabindo Pillai authored
[Why&How] To enable automated testing through IGT, expose an API that is accessible through debugfs to query current status of SubVP feature. Reviewed-by:
Alvin Lee <alvin.lee2@amd.com> Acked-by:
Aurabindo Pillai <aurabindo.pillai@amd.com> Tested-by:
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Iswara Nagulendran authored
[HOW&WHY] Reading the value from DP_EDP_BACKLIGHT_MODE_SET_REGISTER, DPCD 0x721 before setting the BP_EDP_PANEL_LUMINANC_CONTROL_ENABLE bit to ensure there are no accidental overwrites. Reviewed-by:
Sreeja Golui <sreeja.golui@amd.com> Reviewed-by:
Harry Vanzylldejong <harry.vanzylldejong@amd.com> Acked-by:
Iswara Nagulendran <iswara.nagulendran@amd.com> Tested-by:
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Michael Strauss authored
[WHY] Currently causes some DP link layer failures, backing out until the failures are root caused. Reviewed-by:
Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Acked-by:
Michael Strauss <michael.strauss@amd.com> Tested-by:
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Ilya Bakoulin authored
[Why] LUT params are not cleared after setting blend TF, which can lead to same params being used for the shaper, if the shaper func is bypassed. [How] Set lut_params to NULL after program_1dlut. Reviewed-by:
Krunoslav Kovac <krunoslav.kovac@amd.com> Acked-by:
Ilya Bakoulin <ilya.bakoulin@amd.com> Tested-by:
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Samson Tam authored
[Why] In cases where number of pipes available is less than num_opp, there will opp instances that are null [How] Add null check to skip over these opp instances Fixes: 40de8403 ("drm/amd/display: Update OPP counter from new interface") Reviewed-by:
Samson Tam <samson.tam@amd.com> Tested-by:
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Alvin Lee authored
Provide DCN32 specific sequence and update DCN30 sequence Reviewed-by:
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Samson Tam authored
[Why] Helper function calculates num_ways using 32-bit. But is returned as 8-bit. If num_ways exceeds 8-bit, then it reports back the incorrect num_ways and erroneously uses MALL when it should not [How] Make returned value 32-bit and convert after it checks against caps.cache_num_ways, which is under 8-bit Reviewed-by:
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Rodrigo Siqueira authored
This commit adds the amdgpu_dm_plane_ prefix for all functions in the amdgpu_dm_plane.c. This change enables an easy way to filter code paths via ftrace. Reviewed-by:
Rodrigo Siqueira <rodrigo.siqueira@amd.com> Tested-by:
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Rodrigo Siqueira authored
The ftrace debug feature allows filtering functions based on a prefix, which can be helpful in some complex debug scenarios. The driver can benefit more from this feature if the function name follows some patterns; for this reason, this commit adds the prefix amdgpu_dm_crtc_ to all the functions that do not have it in the amdgpu_dm_crtc.c file. Reviewed-by:
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Rodrigo Siqueira authored
This commit just replaces dc_interrupt_po*r*larity with its correct name, which is dc_interrupt_polarity. Reviewed-by:
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Alex Hung authored
[WHY & HOW] Virtual sink is not audio-capable and this causes kms_hdmi_inject's inject-audio to fail. Set it to HDMI according to EDID. Reviewed-by:
Chao-kai Wang <stylon.wang@amd.com> Acked-by:
Alex Hung <alex.hung@amd.com> Tested-by:
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Alex Hung authored
This reverts commit 4ad3ee5c. [WHY & HOW] Virtual signal is not supported as audio capable by DC. Reviewed-by:
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Sung Joon Kim authored
[why] Bandwidth validation failure on framepack tests. Need to double pixel clock when 3D format is framepack. Also for HDMI displays, we need to keep the ITC flag to 1 by default. [how] Double the pixel clock when using framepack 3D format. Set hdmi ITC bit to 1. Reviewed-by:
Charlene Liu <charlene.liu@amd.com> Acked-by:
Sung Joon Kim <sungkim@amd.com> Tested-by:
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Nicholas Kazlauskas authored
[Why] Intermittent reboot hangs are observed introduced by "Improve x86 and dmub ips handshake". [How] Bring back the commit but fix the polling. Avoid hanging in place forever by bounding the delay and ensure that we still message DMCUB on IPS2 exit to notify driver idle has been cleared. Reviewed-by:
Duncan Ma <duncan.ma@amd.com> Reviewed-by:
Jun Lei <jun.lei@amd.com> Acked-by:
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Wenjing Liu authored
[why] Unify pipe resource management logic in dc resource layer. V2: Add default case for switch. CC: Hamza Mahfooz <hamza.mahfooz@amd.com> Reviewed-by:
Chaitanya Dhere <chaitanya.dhere@amd.com> Signed-off-by:
Wenjing Liu <wenjing.liu@amd.com> Reviewed-by:
Qingqing Zhuo <qingqing.zhuo@amd.com> Tested-by:
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Wenjing Liu authored
[why] Need DML2 to support new pipe resource management APIs. Reviewed-by:
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Swapnil Patel authored
[Why & How] Currently set_default_brightness_aux function uses 5 nits as lower limit to check for valid default_backlight setting. However some newer panels can support even lower default settings Reviewed-by:
Agustin Gutierrez <agustin.gutierrez@amd.com> Acked-by:
Swapnil Patel <swapnil.patel@amd.com> Tested-by:
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George Shen authored
[Why] Certain test equipment vendors check the SDP VSC for colorimetry against the value from the test request during certain DP link layer tests for YCbCr test cases. [How] Update SDP VSC with colorimetry from test automation request. Reviewed-by:
George Shen <george.shen@amd.com> Tested-by:
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Sung Joon Kim authored
[why] Need a helper function to check idle power is allowed so that dc doesn't access any registers that are power-gated. [how] Implement helper function to check idle power optimization. Enable a hook to check if detection is allowed. V2: Add function hooks for set and get idle states. Check if function hook was properly initialized. Reviewed-by:
Nicholas Choi <nicholas.choi@amd.com> Acked-by:
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Nicholas Kazlauskas authored
This reverts commit 1288d702. Causes intermittent hangs during reboot stress testing. Reviewed-by:
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Fangzhi Zuo authored
dcn35 misses .enable_symclk_se hook that makes MST DSC not functional when having multiple FE clk to be enabled. Reviewed-by:
Fangzhi Zuo <jerry.zuo@amd.com> Tested-by:
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Mario Limonciello authored
Currently there are separate but related checks: * amdgpu_device_should_use_aspm() * amdgpu_device_aspm_support_quirk() * amdgpu_device_pcie_dynamic_switching_supported() Simplify into checking whether DPM was enabled or not in the auto case. This works because amdgpu_device_pcie_dynamic_switching_supported() populates that value. Signed-off-by:
Mario Limonciello <mario.limonciello@amd.com> Reviewed-by:
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Mario Limonciello authored
There is no need for every ASIC driver to perform the same check. Move the duplicated code into amdgpu_device_should_use_aspm(). Signed-off-by:
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Mario Limonciello authored
Rather than individual ASICs checking for the quirk, set the quirk at the driver level. Signed-off-by:
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Philip Yang authored
This reverts commit dc427a47. The change prevents migrating the entire range to VRAM because retry fault restore_pages map the remaining system memory range to GPUs. It will work correctly to submit together with partial mapping to GPU patch later. Signed-off-by:
Philip Yang <Philip.Yang@amd.com> Reviewed-by:
Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by:
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Philip Yang authored
This reverts commit f9caf6cd. Needed for the next revert patch. Signed-off-by:
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Stylon Wang authored
[Why & How] Fix incomplete copyright notice in DC code. Reviewed-by:
Harry Wentland <harry.wentland@amd.com> Signed-off-by:
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Stylon Wang authored
[Why & How] Fix incomplete copyright notice in DML2 code. Reviewed-by:
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Stylon Wang authored
[Why & How] Add missing/incomplete copyright notice in DMUB files Reviewed-by:
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Lin.Cao authored
Remove restriction of sriov max_pfn so that TBA and TMA can move to high 47 bits address. Regression test: change range alloc flag of libdrm as AMDGPU_VA_RANGE_HIGH and there is no flr occur when testing amdgpu_test of drm. Signed-off-by:
Lin.Cao <lincao12@amd.com> Acked-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
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Srinivasan Shanmugam authored
Fixes the below: drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_svm.c:2073: warning: Function parameter or member 'remap_list' not described in 'svm_range_add' Cc: Felix Kuehling <Felix.Kuehling@amd.com> Cc: Christian König <christian.koenig@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: "Pan, Xinhui" <Xinhui.Pan@amd.com> Signed-off-by:
Srinivasan Shanmugam <srinivasan.shanmugam@amd.com> Reviewed-by:
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Qu Huang authored
In certain types of chips, such as VEGA20, reading the amdgpu_regs_smc file could result in an abnormal null pointer access when the smc_rreg pointer is NULL. Below are the steps to reproduce this issue and the corresponding exception log: 1. Navigate to the directory: /sys/kernel/debug/dri/0 2. Execute command: cat amdgpu_regs_smc 3. Exception Log:: [4005007.702554] BUG: kernel NULL pointer dereference, address: 0000000000000000 [4005007.702562] #PF: supervisor instruction fetch in kernel mode [4005007.702567] #PF: error_code(0x0010) - not-present page [4005007.702570] PGD 0 P4D 0 [4005007.702576] Oops: 0010 [#1] SMP NOPTI [4005007.702581] CPU: 4 PID: 62563 Comm: cat Tainted: G OE 5.15.0-43-generic #46-Ubunt u [4005007.702590] RIP: 0010:0x0 [4005007.702598] Code: Unable to access opcode bytes at RIP 0xffffffffffffffd6. [4005007.702600] RSP: 0018:ffffa82b46d27da0 EFLAGS: 00010206 [4005007.702605] RAX: 0000000000000000 RBX: 0000000000000000 RCX: ffffa82b46d27e68 [4005007.702609] RDX: 0000000000000001 RSI: 0000000000000000 RDI: ffff9940656e0000 [4005007.702612] RBP: ffffa82b46d27dd8 R08: 0000000000000000 R09: ffff994060c07980 [4005007.702615] R10: 0000000000020000 R11: 0000000000000000 R12: 00007f5e06753000 [4005007.702618] R13: ffff9940656e0000 R14: ffffa82b46d27e68 R15: 00007f5e06753000 [4005007.702622] FS: 00007f5e0755b740(0000) GS:ffff99479d300000(0000) knlGS:0000000000000000 [4005007.702626] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [4005007.702629] CR2: ffffffffffffffd6 CR3: 00000003253fc000 CR4: 00000000003506e0 [4005007.702633] Call Trace: [4005007.702636] <TASK> [4005007.702640] amdgpu_debugfs_regs_smc_read+0xb0/0x120 [amdgpu] [4005007.703002] full_proxy_read+0x5c/0x80 [4005007.703011] vfs_read+0x9f/0x1a0 [4005007.703019] ksys_read+0x67/0xe0 [4005007.703023] __x64_sys_read+0x19/0x20 [4005007.703028] do_syscall_64+0x5c/0xc0 [4005007.703034] ? do_user_addr_fault+0x1e3/0x670 [4005007.703040] ? exit_to_user_mode_prepare+0x37/0xb0 [4005007.703047] ? irqentry_exit_to_user_mode+0x9/0x20 [4005007.703052] ? irqentry_exit+0x19/0x30 [4005007.703057] ? exc_page_fault+0x89/0x160 [4005007.703062] ? asm_exc_page_fault+0x8/0x30 [4005007.703068] entry_SYSCALL_64_after_hwframe+0x44/0xae [4005007.703075] RIP: 0033:0x7f5e07672992 [4005007.703079] Code: c0 e9 b2 fe ff ff 50 48 8d 3d fa b2 0c 00 e8 c5 1d 02 00 0f 1f 44 00 00 f3 0f 1e fa 64 8b 04 25 18 00 00 00 85 c0 75 10 0f 05 <48> 3d 00 f0 ff ff 77 56 c3 0f 1f 44 00 00 48 83 e c 28 48 89 54 24 [4005007.703083] RSP: 002b:00007ffe03097898 EFLAGS: 00000246 ORIG_RAX: 0000000000000000 [4005007.703088] RAX: ffffffffffffffda RBX: 0000000000020000 RCX: 00007f5e07672992 [4005007.703091] RDX: 0000000000020000 RSI: 00007f5e06753000 RDI: 0000000000000003 [4005007.703094] RBP: 00007f5e06753000 R08: 00007f5e06752010 R09: 00007f5e06752010 [4005007.703096] R10: 0000000000000022 R11: 0000000000000246 R12: 0000000000022000 [4005007.703099] R13: 0000000000000003 R14: 0000000000020000 R15: 0000000000020000 [4005007.703105] </TASK> [4005007.703107] Modules linked in: nf_tables libcrc32c nfnetlink algif_hash af_alg binfmt_misc nls_ iso8859_1 ipmi_ssif ast intel_rapl_msr intel_rapl_common drm_vram_helper drm_ttm_helper amd64_edac t tm edac_mce_amd kvm_amd ccp mac_hid k10temp kvm acpi_ipmi ipmi_si rapl sch_fq_codel ipmi_devintf ipm i_msghandler msr parport_pc ppdev lp parport mtd pstore_blk efi_pstore ramoops pstore_zone reed_solo mon ip_tables x_tables autofs4 ib_uverbs ib_core amdgpu(OE) amddrm_ttm_helper(OE) amdttm(OE) iommu_v 2 amd_sched(OE) amdkcl(OE) drm_kms_helper syscopyarea sysfillrect sysimgblt fb_sys_fops cec rc_core drm igb ahci xhci_pci libahci i2c_piix4 i2c_algo_bit xhci_pci_renesas dca [4005007.703184] CR2: 0000000000000000 [4005007.703188] ---[ end trace ac65a538d240da39 ]--- [4005007.800865] RIP: 0010:0x0 [4005007.800871] Code: Unable to access opcode bytes at RIP 0xffffffffffffffd6. [4005007.800874] RSP: 0018:ffffa82b46d27da0 EFLAGS: 00010206 [4005007.800878] RAX: 0000000000000000 RBX: 0000000000000000 RCX: ffffa82b46d27e68 [4005007.800881] RDX: 0000000000000001 RSI: 0000000000000000 RDI: ffff9940656e0000 [4005007.800883] RBP: ffffa82b46d27dd8 R08: 0000000000000000 R09: ffff994060c07980 [4005007.800886] R10: 0000000000020000 R11: 0000000000000000 R12: 00007f5e06753000 [4005007.800888] R13: ffff9940656e0000 R14: ffffa82b46d27e68 R15: 00007f5e06753000 [4005007.800891] FS: 00007f5e0755b740(0000) GS:ffff99479d300000(0000) knlGS:0000000000000000 [4005007.800895] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [4005007.800898] CR2: ffffffffffffffd6 CR3: 00000003253fc000 CR4: 00000000003506e0 Signed-off-by:
Qu Huang <qu.huang@linux.dev> Signed-off-by:
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Tao Zhou authored
PMFW is responsible for RAS error reset in some conditions, driver can skip the operation. v2: add check for ras->in_recovery, it's set earlier than amdgpu_in_reset. v3: fix error in gpu reset check. Signed-off-by:
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Tao Zhou authored
Enable it by default on APU platform. Signed-off-by:
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Lang Yu authored
Otherwise IB test would fail during GPU reset. Signed-off-by:
Lang Yu <Lang.Yu@amd.com> Reviewed-by:
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