- 28 Nov, 2012 40 commits
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Marcin Slusarz authored
Copy/pasted from nouveau_gem_new. Signed-off-by:
Marcin Slusarz <marcin.slusarz@gmail.com> Signed-off-by:
Ben Skeggs <bskeggs@redhat.com>
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Marcin Slusarz authored
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Martin Peres authored
It fixes a bug that would have been introduced when adding more sudevs/engines. Signed-off-by:
Martin Peres <martin.peres@labri.fr> Signed-off-by:
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Ben Skeggs authored
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Ben Skeggs authored
NVIDIA also appear to use the same class on Fermi/Kepler for PPP. Will allow use of the engine if firmware (nvXX_fuc086) provided. Signed-off-by: -
Maarten Lankhorst authored
Will allow use of the engine if firmware (nvXX_fuc086) provided. Signed-off-by:
Maarten Lankhorst <maarten.lankhorst@canonical.com> Signed-off-by:
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Maarten Lankhorst authored
Will allow use of the engine if firmware (nvXX_fuc085) provided. Signed-off-by:
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Maarten Lankhorst authored
Will allow use of the engine if firmware (nvXX_fuc084) provided. Signed-off-by:
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Ben Skeggs authored
Later chipsets use falcon anyway, and I can't currently see a good need for a shared base class. PPP will get the same treatment once Maarten's patches are merged. Signed-off-by: -
Ben Skeggs authored
No support for the class yet, but will be pulled in with Maarten's Fermi vdec patches. The Kepler PPP class is identical. Signed-off-by: -
Ben Skeggs authored
Will allow use of the engine if firmware (nvXX_fuc085) provided. Signed-off-by: -
Ben Skeggs authored
Will allow use of the engine if firmware (nvXX_fuc084) provided. Signed-off-by: -
Ben Skeggs authored
Previously, if either vram/gart handles were specified as ~0, the ioctl call would fail. In order to hack engine selection into the ioctl for kepler, we now define (fb_ctxdma_handle == ~0) to mean "engine mask is in tt_ctxdma_handle". This approach also allows new userspace to detect lack of support for non-PGRAPH channels on older kernels. Signed-off-by: -
Ben Skeggs authored
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Ben Skeggs authored
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Ben Skeggs authored
nv50_fb_trap() will now be called automagically by the mc intr handler, rather than each engine's handler having to check for traps manually. Signed-off-by: -
Ben Skeggs authored
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Ben Skeggs authored
nva3/nvc0 are using falcon, nve0 is now using engine directly. Signed-off-by: -
Ben Skeggs authored
Reviewed-by:
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Ben Skeggs authored
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Ben Skeggs authored
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Ben Skeggs authored
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Dave Airlie authored
This is a precursor to dynamic power management support for nouveau, we need to use pm ops for that, so first convert the driver to using pm ops interfaces. Signed-off-by:
Dave Airlie <airlied@redhat.com> Signed-off-by:
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Dave Airlie authored
This is required to decide if we can auto-powerdown and how to implement it. Signed-off-by:
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Ben Skeggs authored
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Ben Skeggs authored
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Ben Skeggs authored
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Ben Skeggs authored
Ported from original nv50 commit by Christoph, with added support for the setting on later chipsets. Signed-off-by: -
Ben Skeggs authored
Unused, and caused a race with evo_sync(). Will revisit using it properly later on. Signed-off-by: -
Ben Skeggs authored
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Ben Skeggs authored
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Ben Skeggs authored
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Ben Skeggs authored
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Ben Skeggs authored
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Ben Skeggs authored
Currently unused, but checkpointing the merged head handling routines. Signed-off-by: -
Ben Skeggs authored
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Ben Skeggs authored
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Ben Skeggs authored
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Ben Skeggs authored
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Ben Skeggs authored
This is like we do on nv50:nvd9 already. There's been no problems seen yet with using this *seemingly* scratch register to store the value, but we won't be able to do this anymore once nv50's code is merged. Signed-off-by:
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