- 03 Oct, 2019 40 commits
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Kent Russell authored
These are the offsets for CKSVII2C1, and match up with the values already added for CKSVII2C v2: Don't remove some of the CSKVII2C values Signed-off-by:
Kent Russell <kent.russell@amd.com> Reviewed-by:
Andrey Grodzovsky <andrey.grodzovsky@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Yong Zhao authored
The old name is prone to confusion. The register offset is for a RLC queue rather than a SDMA engine. The value is not a base address, but a register offset. Signed-off-by:
Yong Zhao <Yong.Zhao@amd.com> Reviewed-by:
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Yong Zhao authored
HW folks have confirm that we should not touch RESUME_CTX of SDMA*_GFX_CONTEXT_CNTL when manipulating RLC queues. Signed-off-by:
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Navid Emamdoost authored
In dcn*_create_resource_pool the allocated memory should be released if construct pool fails. Reviewed-by:
Harry Wentland <harry.wentland@amd.com> Signed-off-by:
Navid Emamdoost <navid.emamdoost@gmail.com> Signed-off-by:
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shaoyunl authored
Add device info for both navi12 PF and VF Signed-off-by:
shaoyunl <shaoyun.liu@amd.com> Reviewed-by:
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Christian König authored
We should print the error only when we are hotplugged and crash basically all userspace applications. Signed-off-by:
Christian König <christian.koenig@amd.com> Reviewed-by:
Emily Deng <Emily.Deng@amd.com> Acked-by:
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Christian König authored
When CPU access is needed we should tell that to amdgpu_bo_create_reserved() or otherwise the access is denied later on. Signed-off-by:
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Evan Quan authored
To pair the latest SMU firmware. Signed-off-by:
Evan Quan <evan.quan@amd.com> Reviewed-by:
Le Ma <Le.Ma@amd.com> Signed-off-by:
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Tao Zhou authored
add comments to clarify why checking GFX IP BLOCK for each ras interrupt callback Signed-off-by:
Tao Zhou <tao.zhou1@amd.com> Reviewed-by:
Guchun Chen <guchun.chen@amd.com> Signed-off-by:
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Tao Zhou authored
common gmc_ecc_late_init can be shared among all generations of gmc v2: rename gmc_ecc_late_init to gmc_ras_late_init Signed-off-by:
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Tao Zhou authored
it's more suitable to put xgmi ras fini in xgmi block Signed-off-by:
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Tao Zhou authored
it's more suitable to put mmhub ras fini in mmhub block Signed-off-by:
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Tao Zhou authored
it's more suitable to put umc ras fini in umc block Signed-off-by:
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Tao Zhou authored
add ras fini for xgmi to cleanup xgmi ras framework Signed-off-by:
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Tao Zhou authored
add a common nbio ras fini implementation to cleanup nbio ras framework Signed-off-by:
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Tao Zhou authored
simplify the code of accessing to eeprom_control struct Signed-off-by:
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Tao Zhou authored
gfx_ras_late_init can get the info by itself Signed-off-by:
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Tao Zhou authored
umc_ras_late_init can get the info by itself Signed-off-by:
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Tao Zhou authored
sdma_ras_fini can be shared among all generations of sdma Signed-off-by:
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Tao Zhou authored
gfx_ras_fini can be shared among all generations of gfx Signed-off-by:
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Tao Zhou authored
gmc_ras_fini can be shared among all generations of gmc Signed-off-by:
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Tao Zhou authored
mmhub_ras_if is relevant to mmhub Signed-off-by:
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Tao Zhou authored
remove mmhub_funcs in adev Signed-off-by:
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Tao Zhou authored
put mmhub_funcs and ras_if pointer into mmhub struct Signed-off-by:
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Tao Zhou authored
umc_ras_if is relevant to umc Signed-off-by:
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Tao Zhou authored
simplify code logic and refine return value v2: remove unused error source code Signed-off-by:
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Tao Zhou authored
sdma ras ecc functions can be reused among all sdma generations Signed-off-by:
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Tao Zhou authored
gfx ras ecc common functions could be reused among all gfx generations Signed-off-by:
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Tao Zhou authored
move umc ras irq functions from gmc v9 to generic umc block, these functions are relevant to umc and they can be shared among all generations of umc Signed-off-by:
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Tao Zhou authored
change struct ras_err_data *err_data to void *err_data, align with umc code and the callback's declaration in each ras block could pay no attention to the structure type Signed-off-by:
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Monk Liu authored
issue: the UMC6 h/w bug is that when MCLK is doing the switch in the middle of a page access being preempted by high priority client (e.g. DISPLAY) then UMC and the mclk switch would stuck there due to deadlock how: fixed by disabling auto PreChg for UMC to avoid high priority client preempting other client's access on the same page, thus the deadlock could be avoided v2: put the patch in callback of UMC6 v3: rename the callback to "init_registers" Signed-off-by:
Monk Liu <Monk.Liu@amd.com> Reviewed-by:
Hawking Zhang <hawking.zhang@amd.com> Signed-off-by:
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Marek Olšák authored
Never used. Signed-off-by:
Marek Olšák <marek.olsak@amd.com> Acked-by:
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Alex Deucher authored
fetch both the vram type and width in one function call. This avoids having to parse the same data table twice to get the two pieces of data. Reviewed-by:
Xiaojie Yuan <xiaojie.yuan@amd.com> Signed-off-by:
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Alex Deucher authored
The index is stored in scratch register 4 after asic init. Use that index. No functional change since all asics in a family use the same type of vram (G5, G6, HBM) and that is all we use at the monent, but if we ever need to query other info, we will now have the proper index. v2: module array is variable sized, handle that. v3: fix off by one in array handling Reviewed-by:
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Alex Deucher authored
It's apparently needed in some configurations. Reviewed-by:
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Shirish S authored
log the response status related error to the driver's debug log since psp response status is not 0 even though there was no problem while the command was submitted. This warning misleads, hence this change. Signed-off-by:
Shirish S <shirish.s@amd.com> Acked-by:
Huang Rui <ray.huang@amd.com> Reviewed-by:
Feifei Xu <Feifei.Xu@amd.com> Signed-off-by:
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Kevin Wang authored
remove duplicate macro of smu_get_uclk_dpm_states fix commit: drm/amd/powerplay: add the interface for getting ultimate frequency v3 Signed-off-by:
Kevin Wang <kevin1.wang@amd.com> Reviewed-by:
Kenneth Feng <kenneth.feng@amd.com> Reviewed-by:
Prike Liang <Prike.Liang@amd.com> Signed-off-by:
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Jesse Zhang authored
When compute fence did not signal, compute ring cannot detect hardware hang because its timeout value is set to be infinite by default. In SR-IOV and passthrough mode, if user does not declare custome timeout value for compute ring, then use gfx ring timeout value as default. So that when there is a ture hardware hang, compute ring can detect it. Signed-off-by:
Jesse Zhang <zhexi.zhang@amd.com> Reviewed-by:
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chen gong authored
Renoir need to use mode2 mode to implement GPU RESET Signed-off-by:
chen gong <curry.gong@amd.com> Reviewed-by:
Aaron Liu <aaron.liu@amd.com> Reviewed-by:
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chen gong authored
Changes to function "smu_suspend" in amdgpu_smu.c is a workaround. We should get real information about if baco is enabled or not, while we always consider APU SMU feature as enabled in current code. I know APU do not support baco mode for GPU reset, so I use "adev->flags" to skip function "smu_feature_is_enabled". Signed-off-by:
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