- 27 Mar, 2015 3 commits
-
-
Baruch Siach authored
This makes the error message much more useful. Signed-off-by:
Baruch Siach <baruch@tkos.co.il> Signed-off-by:
Linus Walleij <linus.walleij@linaro.org>
-
Baruch Siach authored
Make pinconf_generic_dt_node_to_map() also scan the dt pin configuration node directly referenced by phandle, not only its child nodes. The "parent scan" feature needs a few other changes: * Move the pinconf_generic_dt_node_to_map() error handling code to a common place, under the 'exit' label. * Move the pins/groups strings count earlier in pinconf_generic_dt_subnode_to_map(), to allow us to bail out early when these properties are missing or wrong Signed-off-by: -
Thomas Petazzoni authored
This commit adds suspend/resume support to the Armada XP pinctrl driver, by simply saving and restoring the MPP registers. Signed-off-by:
Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by:
-
- 25 Mar, 2015 5 commits
-
-
Lee Jones authored
Great for easily determining which mode a pin is operating in. This patch was particularly helpful when debugging a recent GPIO/ Pinctrl disparity issue. Before: $ cat /sys/kernel/debug/pinctrl/<pin-controller>/pinconf-pins pin 33 (PIO4[1]):[OE:0,PU:0,OD:0] [retime:0,invclk:0,clknotdat:0,de:0,rt-clk:0,rt-delay:0] After [GPIO]: $ cat /sys/kernel/debug/pinctrl/<pin-controller>/pinconf-pins pin 33 (PIO4[1]):[OE:0,PU:0,OD:0] GPIO [retime:0,invclk:0,clknotdat:0,de:0,rt-clk:0,rt-delay:0] After [Alt]: $ cat /sys/kernel/debug/pinctrl/<pin-controller>/pinconf-pins pin 33 (PIO4[1]):[OE:0,PU:0,OD:0] Alt Fn 2 [retime:0,invclk:0,clknotdat:0,de:0,rt-clk:0,rt-delay:0] Acked-by:Maxime Coquelin <maxime.coquelin@st.com> Signed-off-by:
Lee Jones <lee.jones@linaro.org> Signed-off-by:
-
Lee Jones authored
Until now ST's pinconf_dbg_show() call-back has displayed the PIO alternate function direction, which is only relevant if a pin is operating in an alternate function mode i.e not GPIO mode. If a pin is in GPIO mode its direction is both set and status is obtained by a completely different/unrelated bunch of registers. This change ensures that the correct pin direction is shown, even if a pin is operating in GPIO mode. Reported-by:
Olivier Clergeaud <olivier.clergeaud@st.com> Acked-by:
-
Lee Jones authored
ST's hardware differentiates between GPIO mode and Pinctrl alternate functions. When a pin is in GPIO mode, there are dedicated registers to set and obtain direction status. However, If a pin's alternate function is in use then the direction is set and status is derived from a bunch of syscon registers. The issue is; until now there was a lack of parity between the two. For example: Catting the two following information sources could result in conflicting information (output has been snipped for simplicity): $ cat /sys/kernel/debug/gpio GPIOs 32-39, platform/961f080.pin-controller-sbc, PIO4: gpio-33 (? ) out hi $ cat /sys/kernel/debug/pinctrl/<pin-controller>/pinconf-pins pin 33 (PIO4[1]):[OE:0,PU:0,OD:0] [retime:0,invclk:0,clknotdat:0,de:0,rt-clk:0,rt-delay:0] In this example GPIO-33 is a GPIO controlled LED, which is set for output, as you'd expect. However, when the same information is drafted from Pinctrl, it clearly states that OE (Output Enable) is not set i.e. the pin is set for input. This is because OE normally only represents alternate functions and has no bearing on how the pin operates when in Alt-0 (GPIO mode). This patch changes the current semantics and provides a parity link between the two subsystems. The get_direction() call-back firstly determines which function a pin is operating in, then uses the appropriate helpers for that mode. Reported-by: -
Lee Jones authored
st_get_pio_control() will be used by subsequent calls which are to be located above its original position. This is required to prevent the need for an unnecessary forward-declaration/prototype. Acked-by:
-
Lee Jones authored
This call fetches the numerical function value a specified pin is currently operating in. Function zero is more often than not the GPIO function. Greater than zero values represent an alternative function. You'd need to either look those up in the Device Tree sources or the Programmer's Manual. Acked-by:
-
- 19 Mar, 2015 1 commit
-
-
Stefan Agner authored
Optional fields are set to -1 by various preprocessor macros. Make sure the fields can actually store them. Signed-off-by:
Stefan Agner <stefan@agner.ch> Acked-by:
Stephen Warren <swarren@nvidia.com> Tested-by:
-
- 18 Mar, 2015 31 commits
-
-
Baruch Siach authored
pinconf_generic_dt_node_to_map() scans only subnodes of the pinctrl-0 pahndle, not the referenced node itself. Change the example nodes to match. Signed-off-by:
-
Axel Lin authored
Also make the table a bit compact. Signed-off-by:
Axel Lin <axel.lin@ingics.com> Acked-by:
Hongzhou Yang <hongzhou.yang@mediatek.com> Signed-off-by:
-
Axel Lin authored
Prefer devm_kcalloc over devm_kzalloc with multiply. Signed-off-by:
-
Axel Lin authored
Fix below build error: CC drivers/pinctrl/mediatek/pinctrl-mt8135.o In file included from drivers/pinctrl/mediatek/pinctrl-mt8135.c:24:0: drivers/pinctrl/mediatek/pinctrl-mtk-mt8135.h:19:32: fatal error: pinctrl-mtk-common.h: No such file or directory compilation terminated. make[3]: *** [drivers/pinctrl/mediatek/pinctrl-mt8135.o] Error 1 make[2]: *** [drivers/pinctrl/mediatek] Error 2 make[1]: *** [drivers/pinctrl] Error 2 make: *** [drivers] Error 2 Signed-off-by:
Matthias Brugger <matthias.bgg@gmail.com> Reviewed-by:
Guenter Roeck <linux@roeck-us.net> Acked-by:
-
Yingjoe Chen authored
ARM64 maintainer doesn't want to add MACH_* for each SoC. Adjust mt8173 pinctrl kconfig entry so user can manually select it. Also make PINCTRL_MT8135 selectable when COMPILE_TEST is enabled. Signed-off-by:
Yingjoe Chen <yingjoe.chen@mediatek.com> Signed-off-by:
-
Axel Lin authored
Remove erroneous kfree for memory allocated by devm_kzalloc Signed-off-by:
-
Guenter Roeck authored
Fix the following build failure: In file included from drivers/pinctrl/mediatek/pinctrl-mt8135.c:24:0: drivers/pinctrl/mediatek/pinctrl-mtk-mt8135.h:19:32: fatal error: pinctrl-mtk-common.h: No such file or directory seen when building arm:multi_v7_defconfig. Fixes: 94097d89c145 ("pinctrl: mediatek: Add Pinctrl/GPIO driver for mt8135.") Cc: Hongzhou Yang <hongzhou.yang@mediatek.com> Signed-off-by:Paul Walmsley <paul@pwsan.com> Signed-off-by:
-
Geert Uytterhoeven authored
The r8a7790 platform is now DT-only, the driver doesn't need to match platform devices by name anymore. Remove the corresponding platform_device_id entry. Signed-off-by:
Geert Uytterhoeven <geert+renesas@glider.be> Acked-by:
Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by:
-
Geert Uytterhoeven authored
The emev2 platform is now DT-only, the driver doesn't need to match platform devices by name anymore. Remove the corresponding platform_device_id entry. Signed-off-by:
-
Geert Uytterhoeven authored
Currently all PFC registers lie in low 32-bit address space. Hence use u32 instead of unsigned long to store PFC register addresses in pinctrl tables. All calculations of virtual addresses use a phys_addr_t intermediate, so we know where to add an offset if the 32-bit assumption ever becomes false. While this doesn't impact 32-bit builds, it would save ca. 7 KiB on a 64-bit shmobile_defconfig kernel. Signed-off-by:
-
Geert Uytterhoeven authored
All other loops over sh_pfc_soc_info.data_regs[] use pinmux_data_reg.regwidth as the sentinel, which is safer as zero is never a valid regwidth value (reg could be zero if we start using it to store an offset). Signed-off-by:
-
Geert Uytterhoeven authored
As register and field widths and offsets are in the range 1..32, use unsigned int (mostly replacing unsigned long) to store them in local variables and for passing them around. Move to one variable per line, move variables to the beginning of the block where they are used, and drop superfluous initializations while we are at it. Signed-off-by:
-
Geert Uytterhoeven authored
Register and field widths are in the range 1..32. Storing them in the pinctrl data in (arrays of) unsigned long wastes space. This decreases the size of a (32-bit) shmobile_defconfig kernel supporting 7 SoCs by 26460 bytes. Signed-off-by:
-
Ken Xue authored
KERNCZ GPIO is a new IP from AMD. it can be implemented in both x86 and ARM. Current driver patch only support GPIO in x86. Signed-off-by:
Ken Xue <Ken.Xue@amd.com> [Moved back to <linux/gpio.h> header] Signed-off-by:
-
Baruch Siach authored
Signed-off-by:
-
Baruch Siach authored
The callback function signature has changed in commit a5818a8b (pinctrl: get_group_pins() const fixes) Fixes: a5818a8b ('pinctrl: get_group_pins() const fixes') Cc: Stephen Warren <swarren@nvidia.com> Signed-off-by:
-
Abhilash Kesavan authored
The alive pin controller on exynos7 does not support external gpio interrupts. Hence, remove the eint_gpio_init call-back for it. This fixes the following error message seen during exynos7 boot-up: "samsung-pinctrl 10580000.pinctrl: irq number not available" Signed-off-by:
Abhilash Kesavan <a.kesavan@samsung.com> Acked-by:
Tomasz Figa <tomasz.figa@gmail.com> Signed-off-by:
-
Ray Jui authored
This adds the initial support of the Broadcom Cygnus GPIO/PINCONF driver that supports all 3 GPIO controllers on Cygnus including the ASIU GPIO controller, the chipCommonG GPIO controller, and the always-on GPIO controller. Basic PINCONF configurations such as bias pull up/down, and drive strength are also supported in this driver. Pins from the ASIU GPIO controller can be individually muxed to GPIO function, through interaction with the Cygnus IOMUX controller Signed-off-by:
Ray Jui <rjui@broadcom.com> Reviewed-by:
Scott Branden <sbranden@broadcom.com> Tested-by:
Dmitry Torokhov <dtor@chromium.org> Signed-off-by:
-
Ray Jui authored
Document the GPIO/PINCONF device tree binding for Broadcom Cygnus SoC Signed-off-by:
-
Baruch Siach authored
Make the example code consistent wrt local function and struct definitions. Signed-off-by:
-
Baruch Siach authored
This API has changed in commit 6e5e959d (pinctrl: API changes to support multiple states per device). Fixes: 6e5e959d ('pinctrl: API changes to support multiple states per device') Cc: Stephen Warren <swarren@nvidia.com> Signed-off-by:
-
Baruch Siach authored
Commit 03e9f0ca (pinctrl: clean up after enable refactoring) updated the documentation to remove mention of disable(), and rename enable() to set_mux(). One in-text mention was forgotten. Fix this. Fixes: 03e9f0ca ('pinctrl: clean up after enable refactoring') Signed-off-by:
-
Hongzhou Yang authored
Due to pinconf_generic_parse_dt_config() API changes in pinctrl devel branch, add one parameter to fix build error. Also fix warning: drivers/pinctrl/mediatek/pinctrl-mtk-common.c:718:3: warning: too many arguments for format [-Wformat-extra-args] dev_err(&pdev->dev, "only support pins-are-numbered format\n", ret); ^ by removing extra parameter when calling dev_err in mtk_pctrl_init. Signed-off-by: -
Yingjoe Chen authored
MTK EINT does not support generating interrupt on both edges. Emulate this by changing edge polarity while enable irq, set types and interrupt handling. This follows an example of drivers/gpio/gpio-mxc.c. Signed-off-by:
Chaotian Jing <chaotian.jing@mediatek.com> Acked-by:
-
Hongzhou Yang authored
Add mt8173 support using mediatek common pinctrl driver. MT8173 have a different ies_smt setting register than mt8135, so adding this support to common code. Signed-off-by:
-
Maoguang Meng authored
MTK SoC support external interrupt(EINT) from most SoC pins. Add EINT support to pinctrl driver. Signed-off-by:
Maoguang Meng <maoguang.meng@mediatek.com> Signed-off-by:
-
Hongzhou Yang authored
The mediatek SoCs have GPIO controller that handle both the muxing and GPIOs. The GPIO controller have pinmux, pull enable, pull select, direction and output high/low control. This driver include common driver and mt8135 part. The common driver include the pinctrl driver and GPIO driver. The mt8135 part contain its special device data. Signed-off-by:
-
Hongzhou Yang authored
Add devicetree bindings for Mediatek SoC pinctrl driver. Signed-off-by:
Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by:
-
Geert Uytterhoeven authored
As PFC registers are either 8, 16, or 32 bits wide, use u32 (mostly replacing unsigned long) to store (parts of) register values and masks. Switch the shadow register operations from {set,clear}_bit() to plain C bit operations, as the former can operate on long data only. Signed-off-by: -
Ray Jui authored
This adds the initial driver support for the Broadcom Cygnus IOMUX controller. The Cygnus IOMUX controller supports group based mux configuration but allows certain pins to be muxed to GPIO individually Signed-off-by:
-
Ray Jui authored
Device tree binding documentation for Broadcom Cygnus IOMUX driver Signed-off-by:
-
