- 12 Mar, 2021 40 commits
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Bjorn Andersson authored
The PM8150 comes with everything the RTC needs, so let's just leave it enabled instead of having to explicitly enable it for all boards. In effect this patch enables the RTC on the SM8150 MTP and the SM8250 HDK. Acked-by:
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by:
Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210106001004.4081508-1-bjorn.andersson@linaro.orgSigned-off-by:
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Vinod Koul authored
SM8350-MTP features PM8350, PM8350B, PM8350C, PMK8350, PMR735A and PMR735B. PMICs Add the dtsi for these PMICs to MTP. Signed-off-by:
Vinod Koul <vkoul@kernel.org> Link: https://lore.kernel.org/r/20210312052737.3558801-9-vkoul@kernel.orgSigned-off-by:
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Vinod Koul authored
Add base DTS file for PMR735B along with GPIO node Signed-off-by:
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Vinod Koul authored
Add base DTS file for PMR735A along with GPIO node Signed-off-by:
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Vinod Koul authored
Add base DTS file for PM8350C along with GPIO node Signed-off-by:
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Vinod Koul authored
Add base DTS file for PM8350B along with GPIO node Signed-off-by:
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Vinod Koul authored
Add base DTS file for PM8350 along with GPIO node Signed-off-by:
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Vinod Koul authored
Add base DTS file for PMK8350 along with GPIO node Signed-off-by:
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Vinod Koul authored
Add SPMI node found in SM8350 SoC Signed-off-by:
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Srinivas Kandagatla authored
WSA881x powerdown pin is connected to GPIO1 not gpio2, so correct this. This was working so far due to a shift bug in gpio driver, however once that is fixed this will stop working, so fix this! Fixes: 89a32a4e ("arm64: dts: qcom: db845c: add analog audio support") Signed-off-by:
Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Link: https://lore.kernel.org/r/20210309102025.28405-1-srinivas.kandagatla@linaro.orgSigned-off-by:
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Bjorn Andersson authored
Document the SM8350 Hardware Development Kit (HDK). Reviewed-by:
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Stephen Boyd authored
This moved from being trogdor specific to being part of the general sc7180.dtsi SoC file in commit 681a607a ("arm64: dts: qcom: sc7180: Add DisplayPort HPD pin dt node"). Then we dropped the pinconf from the general sc7180.dtsi file in commit 8d079bf2 ("arm64: dts: qcom: sc7180: Drop pinconf on dp_hot_plug_det") and added it back to the trogdor dts file in commit f772081f ("arm64: dts: qcom: sc7180: Add "dp_hot_plug_det" pinconf for trogdor"). As part of this we managed to forget to drop the old copy in the trogdor dts. Let's do it now. Signed-off-by:
Stephen Boyd <swboyd@chromium.org> [dianders: updated desc] Signed-off-by:
Douglas Anderson <dianders@chromium.org> Link: https://lore.kernel.org/r/20210311131008.1.I85fc8146c0ee47e261faa0c54dd621467b81952d@changeidSigned-off-by:
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Shawn Guo authored
The last cell of 'gpio-ranges' should be number of GPIO pins, and in case of qcom platform it should match msm_pinctrl_soc_data.ngpio rather than msm_pinctrl_soc_data.ngpio - 1. This fixes the problem that when the last GPIO pin in the range is configured with the following call sequence, it always fails with -EPROBE_DEFER. pinctrl_gpio_set_config() pinctrl_get_device_gpio_range() pinctrl_match_gpio_range() Fixes: b7e8f433 ("arm64: dts: qcom: Add basic devicetree support for SM8350 SoC") Cc: Vinod Koul <vkoul@kernel.org> Signed-off-by:Shawn Guo <shawn.guo@linaro.org> Link: https://lore.kernel.org/r/20210303033106.549-5-shawn.guo@linaro.orgSigned-off-by:
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Shawn Guo authored
The last cell of 'gpio-ranges' should be number of GPIO pins, and in case of qcom platform it should match msm_pinctrl_soc_data.ngpio rather than msm_pinctrl_soc_data.ngpio - 1. This fixes the problem that when the last GPIO pin in the range is configured with the following call sequence, it always fails with -EPROBE_DEFER. pinctrl_gpio_set_config() pinctrl_get_device_gpio_range() pinctrl_match_gpio_range() Fixes: 16951b49 ("arm64: dts: qcom: sm8250: Add TLMM pinctrl node") Cc: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: -
Shawn Guo authored
The last cell of 'gpio-ranges' should be number of GPIO pins, and in case of qcom platform it should match msm_pinctrl_soc_data.ngpio rather than msm_pinctrl_soc_data.ngpio - 1. This fixes the problem that when the last GPIO pin in the range is configured with the following call sequence, it always fails with -EPROBE_DEFER. pinctrl_gpio_set_config() pinctrl_get_device_gpio_range() pinctrl_match_gpio_range() Fixes: e13c6d14 ("arm64: dts: qcom: sm8150: Add base dts file") Cc: Vinod Koul <vkoul@kernel.org> Signed-off-by: -
Shawn Guo authored
The last cell of 'gpio-ranges' should be number of GPIO pins, and in case of qcom platform it should match msm_pinctrl_soc_data.ngpio rather than msm_pinctrl_soc_data.ngpio - 1. This fixes the problem that when the last GPIO pin in the range is configured with the following call sequence, it always fails with -EPROBE_DEFER. pinctrl_gpio_set_config() pinctrl_get_device_gpio_range() pinctrl_match_gpio_range() Fixes: bc2c8062 ("arm64: dts: qcom: sdm845: Add gpio-ranges to TLMM node") Cc: Evan Green <evgreen@chromium.org> Signed-off-by: -
Rajendra Nayak authored
Add the DT node for the rpmhpd power controller on SC7280 SoCs. Signed-off-by:
Rajendra Nayak <rnayak@codeaurora.org> Reviewed-by:
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Maulik Shah authored
Add cpuidle states for little and big cpus. The latency values are preliminary placeholders and will be updated once testing provides the real numbers. Signed-off-by:
Maulik Shah <mkshah@codeaurora.org> Signed-off-by:
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satya priya authored
Add SPMI PMIC arbiter device to communicate with PMICs attached to SPMI bus. Signed-off-by:
satya priya <skakit@codeaurora.org> Signed-off-by:
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Sai Prakash Ranjan authored
Add APSS (Application Processor Subsystem) watchdog DT node for SC7280 SoC. Signed-off-by:
Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org> Signed-off-by:
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Maulik Shah authored
Add fw reserved memory area for CPUCP (CPUSS control processor) and AOP (Always ON processor) Signed-off-by:
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Sai Prakash Ranjan authored
Adding device node for APPS SMMU available on SC7280 chipset. This is shared among the multiple client devices such as display, video, usb, mmc and others. Signed-off-by:
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Rajendra Nayak authored
Add rpmhcc clock controller node for SC7280. Also add references to rpmhcc clocks in gcc. Signed-off-by:
Taniya Das <tdas@codeaurora.org> Signed-off-by:
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Maulik Shah authored
Add PDC interrupt controller along with apps RSC device. Also add reserved memory for command_db. Signed-off-by:
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Rajendra Nayak authored
Add initial device tree support for the sc7280 SoC and the IDP boards based on this SoC Signed-off-by:
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Rajendra Nayak authored
Document the sc7280 SoC and the IDP board bindings Signed-off-by:
Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/1615461961-17716-2-git-send-email-rnayak@codeaurora.orgSigned-off-by:
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Bjorn Andersson authored
Add initial DTS for the Snapdragon 888 Mobile Hardware Development Kit, aka SM8350 HDK. This initial version describes debug UART, UFS storage, the three USB connectors and remoteprocs. Reviewed-by:
Konrad Dybcio <konrad.dybcio@somainline.org> Reviewed-by:
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Vinod Koul authored
Document the various sony boards for apq8094. These are used in various sony dts files but not documented Signed-off-by:
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Vinod Koul authored
We expect bootloader to full memory details but passing empty values gives warning, so add a default value arch/arm64/boot/dts/qcom/apq8094-sony-xperia-kitakami-karin_windy.dt.yaml: /: memory: False schema does not allow {'device_type': ['memory'], 'reg': [[0, 0, 0, 0]]} Signed-off-by: -
Vinod Koul authored
Document the ipq6018-cp01 board. It was missing leading to warning: arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dt.yaml: /: compatible: 'oneOf' conditional failed, one must be fixed: ['qcom,ipq6018-cp01', 'qcom,ipq6018'] is too short ['qcom,ipq6018-cp01', 'qcom,ipq6018'] is too long Additional items are not allowed ('qcom,ipq6018' was unexpected) Signed-off-by: -
Vinod Koul authored
We expect bootloader to full memory details but passing empty values gives warning, so add a default value arch/arm64/boot/dts/qcom/apq8016-sbc.dt.yaml: /: memory: False schema does not allow {'device_type': ['memory'], 'reg': [[0, 0, 0, 0]]} Signed-off-by: -
Vinod Koul authored
apq8016-sbc is one of the compaitibles for this board, but is not documented, so drop it. This fixes these two warns: arch/arm64/boot/dts/qcom/apq8016-sbc.dt.yaml: /: compatible: ['qcom,apq8016-sbc', 'qcom,apq8016', 'qcom,sbc'] is not valid under any of the given schemas (Possible causes of the failure): arch/arm64/boot/dts/qcom/apq8016-sbc.dt.yaml: /: compatible: ['qcom,apq8016-sbc', 'qcom,apq8016', 'qcom,sbc'] is too long arch/arm64/boot/dts/qcom/apq8016-sbc.dt.yaml: /: compatible:0: 'qcom,apq8016-sbc' is not one of ['qcom,apq8064-cm-qs600', 'qcom,apq8064-ifc6410'] arch/arm64/boot/dts/qcom/apq8016-sbc.dt.yaml: /: compatible:0: 'qcom,apq8016-sbc' is not one of ['qcom,apq8074-dragonboard'] Signed-off-by:
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Douglas Anderson authored
At boot time the following happens: 1. Device core gets ready to probe our SPI driver. 2. Device core applies SPI controller's "default" pinctrl. 3. Device core calls the SPI driver's probe() function which will eventually setup the chip select GPIO as "unasserted". Thinking about the above, we can find: a) For SPI devices that the BIOS inits (Cr50 and EC), the BIOS would have had them configured as "GENI" pins and not as "GPIO" pins. b) It turns out that our BIOS also happens to init these pins as "output" (even though it doesn't need to since they're not muxed as GPIO) but leaves them at the default state of "low". c) As soon as we apply the "default" chip select it'll switch the function to GPIO and stop driving the chip select high (which is how "GENI" was driving it) and start driving it low. d) As of commit 9378f46040be ("UPSTREAM: spi: spi-geni-qcom: Use the new method of gpio CS control"), when the SPI core inits things it inits the GPIO to be "deasserted". Prior to that commit the GPIO was left untouched until first use. e) When the first transaction happens we'll assert the chip select and then deassert it after done. So before the commit to change us to use gpio descriptors we used to have a _really long_ assertion of chip select before our first transaction (because it got pulled down and then the first "assert" was a no-op). That wasn't great but (apparently) didn't cause any real harm. After the commit to change us to use gpio descriptors we end up glitching the chip select line during probe. It would go low and then high with no data transferred. The other side ought to be robust against this, but it certainly could cause some confusion. It's known to at least cause an error message on the EC console and it's believed that, under certain timing conditions, it could be getting the EC into a confused state causing the EC driver to fail to probe. Let's fix things to avoid the glitch. We'll add an extra pinctrl entry that sets the value of the pin to output high (CS deasserted) before doing anything else. We'll do this in its own pinctrl node that comes before the normal pinctrl entries to ensure that the order is correct and that this gets applied before the mux change. This change is in the trogdor board file rather than in the SoC dtsi file because chip select polarity can be different depending on what's hooked up and it doesn't feel worth it to spam the SoC dtsi file with both options. The board file would need to pick the right one anyway. Reviewed-by: -
Sandeep Maheswaram authored
Using pdc interrupts for USB instead of GIC interrupts to support wake up in case xo shutdown. Reviewed-by:
Sandeep Maheswaram <sanm@codeaurora.org> Link: https://lore.kernel.org/r/1594235417-23066-4-git-send-email-sanm@codeaurora.orgSigned-off-by:
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Douglas Anderson authored
This is a trogdor variant. This is mostly a grab from the downstream tree with notable exceptions: - I skip -rev0. This was a super early build and there's no advantage of long term support. - I remove sound node since sound hasn't landed upstream yet. Cc: Gwendal Grignou <gwendal@chromium.org> Cc: Matthias Kaehlcke <mka@chromium.org> Cc: Stephen Boyd <swboyd@chromium.org> Cc: Tzung-Bi Shih <tzungbi@chromium.org> Cc: Judy Hsiao <judyhsiao@chromium.org> Signed-off-by:
Matthias Kaehlcke <mka@chromium.org> Reviewed-by:
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Douglas Anderson authored
This is a trogdor variant. This is mostly a grab from the downstream tree with notable exceptions: - I skip -rev0. This was a super early build and there's no advantage of long term support. - In -rev1 I translate the handling of the USB hub like is done for similar boards. See the difference between the downstream and upstream 'sc7180-trogdor-lazor-r0.dts' for an example. This will need to be resolved when proper support for the USB hub is figured out upstream. - I remove sound node since sound hasn't landed upstream yet. - In incorporate the pending <https://crrev.com/c/2719075> for the keyboard. Cc: Philip Chen <philipchen@google.com> Cc: Matthias Kaehlcke <mka@chromium.org> Cc: Stephen Boyd <swboyd@chromium.org> Cc: Tzung-Bi Shih <tzungbi@chromium.org> Cc: Judy Hsiao <judyhsiao@chromium.org> Signed-off-by:
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Douglas Anderson authored
This is a SKU variant of lazor. Add it. This squashes the downstream patches to support this hardware. NOTES: - The non-touch SKU actually has "innolux,n116bca-ea1" but that driver is still pending in simple-panel. The bindings have been Acked though [1]. Things work well enough with the "innolux,n116bge" timings for now, though. - The wonky special dts just for "-rev4" arguably doesn't need to go upstream since they weren't widely distributed, but since a few people have them we might as well. If it ever causes problems we can delete it. [1] https://lore.kernel.org/r/20210115144345.v2.4.I6889e21811df6adaff5c5b8a8c80fda0669ab3a5@changeid Cc: Stephen Boyd <swboyd@chromium.org> Signed-off-by:
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Matthias Kaehlcke authored
Lazor rev3 and later use the 'lite' version of the SC7180 SoC. Reviewed-by:
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Abhishek Kumar authored
For trogdor, in the latest board-2.bin file, new BDF with variant name GO_LAZOR has been introduced, so we need this property set, for GO_LAZOR BDF to be picked. Cc: Philip Chen <philipchen@chromium.org> Signed-off-by:
Abhishek Kumar <kuabhs@chromium.org> [dianders: adjusted subject line and sort order] Signed-off-by:
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Venkata Lakshmi Narayana Gubba authored
Removed voting for RPMH_RF_CLK2 which is not required as it is getting managed by BT SoC through SW_CTRL line. Cc: Matthias Kaehlcke <mka@chromium.org> Signed-off-by:
Venkata Lakshmi Narayana Gubba <gubbaven@codeaurora.org> Signed-off-by:
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