- 16 Jan, 2020 40 commits
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Wenjing Liu authored
[why] Currently we wait for test pattern after each pipe is programmed. For ODM combined scenario it will cause test pattern is shown on only half screen for 1 frame. This is not desirable. [how] No wait between odm pipe programming, only wait after all pipes are programmed. Signed-off-by:
Wenjing Liu <Wenjing.Liu@amd.com> Reviewed-by:
Tony Cheng <Tony.Cheng@amd.com> Acked-by:
Harry Wentland <harry.wentland@amd.com> Acked-by:
Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Anthony Koo authored
[Why] With different refresh rate panels, the PSR entry/exit time is different since it is dependent on 2 frame entry time today [How] Make static screen num frame entry time to be calculated such that entry time is within 30 ms instead of fixed num frames. Signed-off-by:
Anthony Koo <Anthony.Koo@amd.com> Reviewed-by:
Aric Cyr <Aric.Cyr@amd.com> Acked-by:
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Aric Cyr authored
Signed-off-by:
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Lewis Huang authored
[Why] DMCU need to wait a vblank to handle psr enter command. When psr exit coming before vblank, the psr exit command will be skip because current psr state is disable. [How] remove psr state condition when psr exit case Signed-off-by:
Lewis Huang <Lewis.Huang@amd.com> Reviewed-by:
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Josip Pavic authored
[Why] IRAM definition needed for versions of DMCU containing ABM 2.4 [How] Pass ABM 2.3 IRAM definition, which is compatible with ABM 2.4, to DMCU when ABM 2.4 FW is detected Signed-off-by:
Josip Pavic <Josip.Pavic@amd.com> Reviewed-by:
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Chris Park authored
Signed-off-by:
Chris Park <Chris.Park@amd.com> Reviewed-by:
Jordan Lazare <Jordan.Lazare@amd.com> Acked-by:
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Sung Lee authored
[Why] DML Initialization was previously done on dcn21_resource initialization. This meant that DML soc struct was populated with hardcoded values. [How] Move DML initialization to after updating bounding box, to use clock table values from SMU. Signed-off-by:
Sung Lee <sung.lee@amd.com> Reviewed-by:
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Charlene Liu authored
Signed-off-by:
Charlene Liu <charlene.liu@amd.com> Reviewed-by:
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George Shen authored
[Why] PHY will sometimes be in bad state on hotplugging display from USB-C dongle. [How] Add additional calls to disable and then enable PHY before link training starts during verify_link_cap. Signed-off-by:
George Shen <george.shen@amd.com> Reviewed-by:
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Wyatt Wood authored
[Why] The DMUB PSR command IDs do not have the correct values. [How] Fix the command IDs and cleanup the formatting. Signed-off-by:
Wyatt Wood <wyatt.wood@amd.com> Reviewed-by:
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Yongqiang Sun authored
Rework surface programming for RN to separate preparing parameters and register programming. Signed-off-by:
Yongqiang Sun <yongqiang.sun@amd.com> Reviewed-by:
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Noah Abradjian authored
[Why] Recent double buffering changes for dcn2 use IX_REG_READ. However, this macro returns the full register value, with the need to manually shift and mask it to retrieve field data. [How] Create new IX_REG_GET macro that handles shift and mask. Use this for double buffering reads instead of IX_REG_READ. Signed-off-by:
Noah Abradjian <noah.abradjian@amd.com> Reviewed-by:
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Wyatt Wood authored
[Why] Moving PSR from DMCU to DMCUB. [How] Cleanup psr spec files and add PSR hw programming files. No functionality is included in this change. Signed-off-by:
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Yongqiang Sun authored
Programming surface flip addresses via dmcub uC for optimizing the data flush. Signed-off-by:
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Noah Abradjian authored
[Why] When rapidly adjusting color temperature, screen tearing was observed. This was due to overwritten values in gamut remap registers. This issue was solved for OCSC and ICSC by alternating between "A" and "B" registers to double buffer the writes. [How] Create new set_gamut_remap and program_gamut_remap for dcn20. Alternate which registers are written to by switching modes each time. Also fixes ICSC mode reg read to use proper data offset. Signed-off-by:
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Wyatt Wood authored
[Why] Moving PSR from DMCU to DMCUB. [How] Add driverside PSR changes required to send inbox messages to fw. These changes are non-functional until the psr structure allocation is uncommented. Signed-off-by:
Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by:
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Noah Abradjian authored
[Why] When rapidly adjusting video brightness, screen tearing was observed. This was due to overwritten values in ICSC registers. In dcn10, this issue had been fixed by implementing double buffering via alternating ICSC modes. However, the second register set used in dcn1 doesn't exist in dcn2. [How] Create new program_input_csc for dcn20. Use ICSC_B registers instead of COMA registers as second set. Signed-off-by:
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Aric Cyr authored
Signed-off-by:
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Dmytro Laktyushkin authored
Add more fields to support upcoming dml versions Signed-off-by:
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by:
Jun Lei <Jun.Lei@amd.com> Acked-by:
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Joseph Gravenor authored
[Why] Don't want to start HW discovery unless we have lost power, as doing rediscovery otherwise is both unnecessary and time consuming. Before this change it takes 40 seconds to go in to suspend, after it takes 27 seconds [How] Accelerated mode gets cleared if we lose power. Only do detection if this register is cleared Signed-off-by:
Joseph Gravenor <joseph.gravenor@amd.com> Reviewed-by:
Eric Yang <eric.yang2@amd.com> Acked-by:
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Wenjing Liu authored
Test pattern should be applied to hardware when exiting set test pattern function. Signed-off-by:
Nikola Cornij <Nikola.Cornij@amd.com> Acked-by:
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Michael Strauss authored
[WHY] 48mhz turn off feature does not work on HDMI and DVI, but the feauture was only blocked on HDMI, this change will apply the same wa on DVI [HOW] Apply workaround for all TMDS signal types (HDMI, DVI single/dual link) Signed-off-by:
Michael Strauss <michael.strauss@amd.com> Reviewed-by:
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Alvin Lee authored
[Why] If dummy pstate latency is 0 we should report the actual pstate support, and not that pstate is always supported. [How] Don't always program pstate support true Signed-off-by:
Alvin Lee <alvin.lee2@amd.com> Reviewed-by:
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abdoulaye berthe authored
Make sure that lttpr_caps has the mode set to repeater. Signed-off-by:
abdoulaye berthe <abdoulaye.berthe@amd.com> Reviewed-by:
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Noah Abradjian authored
[Why] When rapidly adjusting colour properties (e.g. brightness), screen tearing was observed. This was due to overwritten values in OCSC registers. In dcn10, this issue had been fixed by implementing double buffering by alternating OCSC modes. [How] Alternate which OCSC registers are used by switching modes each time. This double buffers the CSC writes. Signed-off-by:
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Nicholas Kazlauskas authored
[Why] We need to ensure that the DMUIF in MMHUBBUB is also in reset so we aren't generating requests while the DMCUB is in reset. [How] Set DMUIF_SOFT_RESET=1 on reset and DMUIF_SOFT_RESET=0 on reset release. Signed-off-by:
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Nicholas Kazlauskas authored
[Why] The inst firmware isn't necessarily fully flushed to framebuffer memory and the DMCUB can hang due to invalid inst being parsed. [How] Like the fix to flush ringbuffer commands before updating the inbox write pointer we need to read back inst memory before writing the CW0 registers. Add a helper to read 64-byte chunks to avoid a large temporary buffer. Read the remaining leftover bytes if the inst_fb isn't fully aligned. Signed-off-by:
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Nicholas Kazlauskas authored
[Why] There's a data race that can occur between when we update the inbox write pointer vs when the memory for the command actually gets flushed from the map to the framebuffer. DMCUB can read stale or partially invalid data when this race occurs. [How] Before updating the write pointer we can read back all pending commands to ensure that we stall for the writes to be flushed to framebuffer. We don't need to worry about choosing HDP vs VM flush with this mechanism. Drop the dmub_srv_cmd_submit() while we're updating this to work correctly since nothing was actually using this API and the caller should be explicit about the API flow here - by doing this on execute we can give some extra time for the flush to finish while preparing other commands. We should try to avoid writing single commands because of this overhead. Signed-off-by:
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Martin Leung authored
[why] While doing seamless boot I made some changes to dcn2 hubbub functions, missed a link [how] link hubbub1 func to hubbub2 usage. It has already been successfully linked in dcn1 and 3. Signed-off-by:
Martin Leung <martin.leung@amd.com> Reviewed-by:
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Nikola Cornij authored
[why] If the specific monitor supports DSC, the secondary link should be disabled, and the other way around, too: if either that monitor or our ASIC doesn't support DSC, the secodary link should be enabled. [how] Add a monitor patch and disable secondary link if that monitor is detected and if ASIC supports DSC, or otherwise enable secondary link. Signed-off-by:
Joshua Aberback <Joshua.Aberback@amd.com> Acked-by:
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Alvin Lee authored
Needed to reprogram vblank_start in dml properly in order to get the correct dlg params to program VTG. Signed-off-by:
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Eric Yang authored
[Why] Previous implementation we may have residual chroma address offset if transition from wa enable -> wa disable. [How] Clear address offset cache when viewport updates. Also update the vp size check condition to account for rotation angle Signed-off-by:
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Aric Cyr authored
Signed-off-by:
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Amanda Liu authored
[why] Upon exiting a fixed active VRR state, the state isn't cleared. This leads to the variable VRR range to be calculated incorrectly. [how] Set fixed active state to false when updating vrr params Signed-off-by:
Amanda Liu <amanda.liu@amd.com> Reviewed-by:
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Rodrigo Siqueira authored
Add registers for handling Post Gamma Color Blending (OCSC), which is useful for conversion from RGB->YUV for HDMI. Reviewed-by:
Leo Li <sunpeng.li@amd.com> Acked-by:
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Nirmoy Das authored
This also replaces old artifacts with a correct one in drm_sched_entity_init() declaration Signed-off-by:
Nirmoy Das <nirmoy.das@amd.com> Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
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Hawking Zhang authored
support check if dirver should try gpu recovery for arcturus Signed-off-by:
Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by:
Guchun Chen <guchun.chen@amd.com> Signed-off-by:
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Hawking Zhang authored
To allow the flexibilty for user to disable gpu recovery in RAS recovery path by module parameter amdgpu_gpu_recovery Signed-off-by:
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Evan Quan authored
NFO: task ocltst:2028 blocked for more than 120 seconds. Tainted: G OE 5.0.0-37-generic #40~18.04.1-Ubuntu echo 0 > /proc/sys/kernel/hung_task_timeout_secs" disables this message. cltst D 0 2028 2026 0x00000000 all Trace: __schedule+0x2c0/0x870 schedule+0x2c/0x70 schedule_preempt_disabled+0xe/0x10 __mutex_lock.isra.9+0x26d/0x4e0 __mutex_lock_slowpath+0x13/0x20 ? __mutex_lock_slowpath+0x13/0x20 mutex_lock+0x2f/0x40 amdgpu_dpm_set_powergating_by_smu+0x64/0xe0 [amdgpu] gfx_v8_0_enable_gfx_static_mg_power_gating+0x3c/0x70 [amdgpu] gfx_v8_0_set_powergating_state+0x66/0x260 [amdgpu] amdgpu_device_ip_set_powergating_state+0x62/0xb0 [amdgpu] pp_dpm_force_performance_level+0xe7/0x100 [amdgpu] amdgpu_set_dpm_forced_performance_level+0x129/0x330 [amdgpu] Fixes: a64c9e15 ("drm/amd/powerplay: cleanup the interfaces for powergate setting through SMU") Signed-off-by:Evan Quan <evan.quan@amd.com> Reported-by:
Rui Teng <Rui.Teng@amd.com> Acked-by:
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Huang Rui authored
The mec ucode will set the CP_HQD_ACTIVE bit while the queue is mapped by MAP_QUEUES packet. So we only need set cp active field for kiq queue. Signed-off-by:
Huang Rui <ray.huang@amd.com> Reviewed-by:
Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by:
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