- 24 Mar, 2021 9 commits
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Hawking Zhang authored
PMFW should be loaded before any operation that may toggling DF-Cstate. otherwsie, tOS has no choice but to locally toggle DF Cstate (i.e. disable DF-Cstate even it already enabled by VBIOS) Signed-off-by:
Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by:
Kevin Wang <kevin1.wang@amd.com> Reviewed-by:
Le Ma <Le.Ma@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Hawking Zhang authored
mmRCC_DEV0_EPF0_STRAP0 offset in aldebaran is changed from arcturus Signed-off-by:
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Hawking Zhang authored
Initialze psp ip function for aldebaran Signed-off-by:
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Hawking Zhang authored
Add callback functions for psp_v13 ring Signed-off-by:
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Hawking Zhang authored
Add callback function to support trusted os loading for psp v13 Signed-off-by:
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Hawking Zhang authored
Add callback function to support sys_drv firmware loading for psp v13 Signed-off-by:
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Hawking Zhang authored
Add callback function to support key database firmware loading for psp v13 Signed-off-by:
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Hawking Zhang authored
Initialize sos microcode for aldebaran Signed-off-by:
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Yong Zhao authored
This gives more information and improves productivity. Signed-off-by:
Yong Zhao <Yong.Zhao@amd.com> Signed-off-by:
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- 10 Mar, 2021 23 commits
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Jay Cornwall authored
Similar to arcturus, but ARCH/ACC VGPRs may now be split unevenly. A new field in SQ_WAVE_GPR_ALLOC tracks the boundary between the two sets of VGPRs. Squash below patches: drm/amdkfd: Use preprocessor for IP-specific trap handler code drm/amdkfd: Fix VGPR restore race in gfx8/gfx9 trap handler drm/amdkfd: Remove duplicated code in gfx9 trap handler drm/amdkfd: Separate ARCH/ACC VGPR restore in trap handler drm/amdkfd: Reverse order of ARCH/ACC VGPR restore in trap handler Signed-off-by:
Jay Cornwall <jay.cornwall@amd.com> Signed-off-by:
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Kevin Wang authored
add sdma firmware load support for soc model v2: drop some emulator leftovers (Alex) Signed-off-by:
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Yong Zhao authored
Add initial KFD support. Signed-off-by:
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Le Ma authored
Set ip blocks and asic family id Signed-off-by:
Evan Quan <evan.quan@amd.com> Signed-off-by:
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Le Ma authored
On aldebaran, mmBIF_SDMA4_DOORBELL_RANGE isn't right next to mmBIF_SDMA3_DOORBELL_RANGE. Signed-off-by:
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Le Ma authored
Add initial sdma support for aldebaran, and this asic has 5 sdma instances. v2: remove adundant condition check Signed-off-by:
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Le Ma authored
Add gfx initial support Signed-off-by:
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Le Ma authored
Set backdoor loading way in current phase v2: change case location to not break other asics Signed-off-by:
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Le Ma authored
Add gfx memory controller support Signed-off-by:
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Le Ma authored
v1: dupilcate mmhub_v1_7.c from mmhub_v1_0.c because mmhub register address for aldebaran is different from existing asics (Le) v2: switch to latest mmhub_v9_4_2 register headers (Hawking) v3: squash in init VM_L2_CNTL3 default value for mmhub v1_7 Signed-off-by:
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Le Ma authored
Initialize aldebaran common ip block Signed-off-by:
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Le Ma authored
Parses asic configurations stored in gpu_info firmware and make them available for driver to use. Signed-off-by:
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Le Ma authored
v1: add aldebaran_reg_base_init function to initialize register base for aldebaran (Le) v2: update VCN HWIP and initialize base offset (James) Signed-off-by:
James Zhu <James.Zhu@amd.com> Reviewed-by:
Leo Liu <leo.liu@amd.com> Acked-by:
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Hawking Zhang authored
v1: re-use arct ip base offset array for aldebaran (Le) v2: create aldebaran ip base offset array for major ip blocks (Hawking) v3: re-use arct VCN ip base offset array for aldebaran (James) v4: correct MP1 ip base offset array (Hawking) v5: update VCN ip base offset array to aldebaran one (Hawking) Signed-off-by:
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Le Ma authored
Add aldebaran in amdgpu_asic_name array and amdgpu_asic_type enum Signed-off-by:
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Hawking Zhang authored
v1: Add vcn v2_6_0 register offset and shift masks in header files (Hawking) v2: Clean up vcn v2_6_0 registers (Alex) v3: update registers (Alex) Signed-off-by:
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Hawking Zhang authored
v1: Add umc v6_7_0 register offset and shift masks in header files (Hawking) v2: Clean up registers (Alex) v3: update registers (Alex) Signed-off-by:
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Hawking Zhang authored
v1: Add thm v13_0_2 register offset and shift masks in header files (Hawking) v2: Clean up thm v13_0_2 registers (Alex) v3: update registers (Alex) Signed-off-by:
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Hawking Zhang authored
Add sdma v4_4_0 register offset and shift masks in header files v2: update registers (Alex) Signed-off-by:
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Hawking Zhang authored
v1: Add smuio v13_0_2 register offset and shift masks in header files (Hawking) v2: Clean up smuio v13_0_2 registers (Alex) v3: update registers (Alex) Signed-off-by:
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Hawking Zhang authored
v1: Add mp v13_0_2 register offset and shift masks in header files (Hawking) v2: Clean up mp v13_0_2 registers (Alex) v3: update registers (Alex) Signed-off-by:
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Hawking Zhang authored
v1: Add mmhub v1_7 register offset and shift masks in header files (Hawking) v2: Clean up mmhub v1_7 registers (Alex) v3: Update registers (Alex) Signed-off-by:
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Hawking Zhang authored
v1: Add gc v9_4_2 register offset and shift masks in header files (Hawking) v2: Clean up gc v9_4_2 registers (Alex) v3: update registers (Alex) Signed-off-by:
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- 05 Mar, 2021 8 commits
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Holger Hoffstätte authored
After fixing nested FPU contexts caused by 41401ac6 we're still seeing complaints about spurious kernel_fpu_end(). As it turns out this was already fixed for dcn20 in commit f41ed88c ("drm/amdgpu/display: use GFP_ATOMIC in dcn20_validate_bandwidth_internal") but never moved forward to dcn21. Signed-off-by:
Holger Hoffstätte <holger@applied-asynchrony.com> Signed-off-by:
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Holger Hoffstätte authored
Commit 41401ac6 added FPU wrappers to dcn21_validate_bandwidth(), which was correct. Unfortunately a nested function alredy contained DC_FP_START()/DC_FP_END() calls, which results in nested FPU context enter/exit and complaints by kernel_fpu_begin_mask(). This can be observed e.g. with 5.10.20, which backported 41401ac6 and now emits the following warning on boot: WARNING: CPU: 6 PID: 858 at arch/x86/kernel/fpu/core.c:129 kernel_fpu_begin_mask+0xa5/0xc0 Call Trace: dcn21_calculate_wm+0x47/0xa90 [amdgpu] dcn21_validate_bandwidth_fp+0x15d/0x2b0 [amdgpu] dcn21_validate_bandwidth+0x29/0x40 [amdgpu] dc_validate_global_state+0x3c7/0x4c0 [amdgpu] The warning is emitted due to the additional DC_FP_START/END calls in patch_bounding_box(), which is inlined into dcn21_calculate_wm(), its only caller. Removing the calls brings the code in line with dcn20 and makes the warning disappear. Fixes: 41401ac6 ("drm/amd/display: Add FPU wrappers to dcn21_validate_bandwidth()") Signed-off-by:
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Gustavo A. R. Silva authored
There is a regular need in the kernel to provide a way to declare having a dynamically sized set of trailing elements in a structure. Kernel code should always use “flexible array members”[1] for these cases. The older style of one-element or zero-length arrays should no longer be used[2]. Refactor the code according to the use of a flexible-array member in struct SISLANDS_SMC_SWSTATE, instead of a one-element array, and use the struct_size() helper to calculate the size for the allocation. Also, this helps with the ongoing efforts to enable -Warray-bounds by fixing the following warnings: drivers/gpu/drm/radeon/si_dpm.c: In function ‘si_convert_power_state_to_smc’: drivers/gpu/drm/radeon/si_dpm.c:2350:20: warning: array subscript 1 is above array bounds of ‘SISLANDS_SMC_HW_PERFORMANCE_LEVEL[1]’ {aka ‘struct SISLANDS_SMC_HW_PERFORMANCE_LEVEL[1]’} [-Warray-bounds] 2350 | smc_state->levels[i].dpm2.MaxPS = (u8)((SISLANDS_DPM2_MAX_PULSE_SKIP * (max_sclk - min_sclk)) / max_sclk); | ~~~~~~~~~~~~~~~~~^~~ drivers/gpu/drm/radeon/si_dpm.c:2351:20: warning: array subscript 1 is above array bounds of ‘SISLANDS_SMC_HW_PERFORMANCE_LEVEL[1]’ {aka ‘struct SISLANDS_SMC_HW_PERFORMANCE_LEVEL[1]’} [-Warray-bounds] 2351 | smc_state->levels[i].dpm2.NearTDPDec = SISLANDS_DPM2_NEAR_TDP_DEC; | ~~~~~~~~~~~~~~~~~^~~ drivers/gpu/drm/radeon/si_dpm.c:2352:20: warning: array subscript 1 is above array bounds of ‘SISLANDS_SMC_HW_PERFORMANCE_LEVEL[1]’ {aka ‘struct SISLANDS_SMC_HW_PERFORMANCE_LEVEL[1]’} [-Warray-bounds] 2352 | smc_state->levels[i].dpm2.AboveSafeInc = SISLANDS_DPM2_ABOVE_SAFE_INC; | ~~~~~~~~~~~~~~~~~^~~ drivers/gpu/drm/radeon/si_dpm.c:2353:20: warning: array subscript 1 is above array bounds of ‘SISLANDS_SMC_HW_PERFORMANCE_LEVEL[1]’ {aka ‘struct SISLANDS_SMC_HW_PERFORMANCE_LEVEL[1]’} [-Warray-bounds] 2353 | smc_state->levels[i].dpm2.BelowSafeInc = SISLANDS_DPM2_BELOW_SAFE_INC; | ~~~~~~~~~~~~~~~~~^~~ drivers/gpu/drm/radeon/si_dpm.c:2354:20: warning: array subscript 1 is above array bounds of ‘SISLANDS_SMC_HW_PERFORMANCE_LEVEL[1]’ {aka ‘struct SISLANDS_SMC_HW_PERFORMANCE_LEVEL[1]’} [-Warray-bounds] 2354 | smc_state->levels[i].dpm2.PwrEfficiencyRatio = cpu_to_be16(pwr_efficiency_ratio); | ~~~~~~~~~~~~~~~~~^~~ drivers/gpu/drm/radeon/si_dpm.c:5105:20: warning: array subscript 1 is above array bounds of ‘SISLANDS_SMC_HW_PERFORMANCE_LEVEL[1]’ {aka ‘struct SISLANDS_SMC_HW_PERFORMANCE_LEVEL[1]’} [-Warray-bounds] 5105 | smc_state->levels[i + 1].aT = cpu_to_be32(a_t); | ~~~~~~~~~~~~~~~~~^~~~~~~ [1] https://en.wikipedia.org/wiki/Flexible_array_member [2] https://www.kernel.org/doc/html/v5.9/process/deprecated.html#zero-length-and-one-element-arrays Link: https://github.com/KSPP/linux/issues/79 Link: https://github.com/KSPP/linux/issues/109Build-tested-by:kernel test robot <lkp@intel.com> Link: https://lore.kernel.org/lkml/603f9a8f.aDLrpMFzzSApzVYQ%25lkp@intel.com/Signed-off-by:
Gustavo A. R. Silva <gustavoars@kernel.org> Signed-off-by:
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Colin Ian King authored
The continue statement in a for-loop is redudant and can be removed. Clean up the code to address this. Addresses-Coverity: ("Continue as no effect") Fixes: b6f91fc1 ("drm/amdgpu/display: buffer INTERRUPT_LOW_IRQ_CONTEXT interrupt work") Signed-off-by:Colin Ian King <colin.king@canonical.com> Signed-off-by:
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Colin Ian King authored
The variable status is being initialized with a value that is never read and it is being updated later with a new value. The initialization is redundant and can be removed. Addresses-Coverity: ("Unused value") Signed-off-by: -
Jiapeng Chong authored
Fix the following coccicheck warnings: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c:956:52-57: WARNING: conversion to bool not needed here. ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c:8311:16-21: WARNING: conversion to bool not needed here. Reported-by:
Abaci Robot <abaci@linux.alibaba.com> Signed-off-by:
Jiapeng Chong <jiapeng.chong@linux.alibaba.com> Signed-off-by:
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Takashi Iwai authored
There seem devices that don't work with the aux channel backlight control. For allowing such users to test with the other backlight control method, provide a new module option, aux_backlight, to specify enabling or disabling the aux backport support explicitly. As default, the aux support is detected by the hardware capability. v2: make the backlight option generic in case we add future backlight types (Alex) BugLink: https://bugzilla.opensuse.org/show_bug.cgi?id=1180749 BugLink: https://gitlab.freedesktop.org/drm/amd/-/issues/1438Reviewed-by:
Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by:
Takashi Iwai <tiwai@suse.de> Signed-off-by:
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Alex Deucher authored
Need to fetch it via aux. Reviewed-by:
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