- 29 Apr, 2024 13 commits
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Arnd Bergmann authored
Merge tag 'tegra-for-6.10-arm-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into soc/dt ARM: tegra: Changes for v6.10-rc1 Adds support for EMC frequency scaling on PAZ100 devices with RAM code 1 and cleans up deprecated device tree properties. * tag 'tegra-for-6.10-arm-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: ARM: tegra: tegra20-ac97: Replace deprecated "gpio" suffix ARM: tegra: paz00: Add emc-tables for ram-code 1 Link: https://lore.kernel.org/r/20240426180519.3972626-3-thierry.reding@gmail.comSigned-off-by:
Arnd Bergmann <arnd@arndb.de>
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Arnd Bergmann authored
Merge tag 'tegra-for-6.10-dt-bindings' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into soc/dt dt-bindings: Changes for v6.10-rc1 Included is one change that adds the dma-coherent flag to the device tree json-schema for host1x on Tegra194 and Tegra234. * tag 'tegra-for-6.10-dt-bindings' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: dt-bindings: display: tegra: Allow dma-coherent on Tegra194 and later Link: https://lore.kernel.org/r/20240426180519.3972626-2-thierry.reding@gmail.comSigned-off-by:
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Arnd Bergmann authored
Merge tag 'sunxi-dt-for-6.10-1' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into soc/dt - added multicolor LED node for pinephone - marked pinephone LEDs to retain status in suspend - DT cleanups & fixes - fixed A64 GPU frequency at 432 MHz - added H616 NMI node - new boards: PocketBook 614 Plus, Tanix TX1 * tag 'sunxi-dt-for-6.10-1' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux: arm64: dts: allwinner: h616: Add NMI device node arm64: dts: allwinner: Add Tanix TX1 support dt-bindings: arm: sunxi: document Tanix TX1 name ARM: dts: sun5i: Add PocketBook 614 Plus support dt-bindings: arm: sunxi: Add PocketBook 614 Plus arm64: dts: allwinner: h616: Fix I2C0 pins arm64: dts: allwinner: a64: Run GPU at 432 MHz arm: dts: allwinner: drop underscore in node names arm64: dts: allwinner: Orange Pi: delete node by phandle arm64: dts: allwinner: drop underscore in node names arm64: dts: allwinner: Pine H64: correctly remove reg_gmac_3v3 arm64: dts: allwinner: pinephone: add multicolor LED node arm64: dts: allwinner: pinephone: Retain LEDs state in suspend Link: https://lore.kernel.org/r/20240426164510.GA101219@jernej-laptopSigned-off-by:
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Arnd Bergmann authored
Merge tag 'renesas-dts-for-v6.10-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into soc/dt Renesas DTS updates for v6.10 (take two) - Add external interrupt (IRQC) support for the RZ/Five SoC, - Add SPI (MSIOF), external interrupt (INTC-EX), and IOMMU support for the R-Car V4M SoC, - Miscellaneous fixes and improvements. * tag 'renesas-dts-for-v6.10-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel: arm64: dts: renesas: r8a779h0: Link IOMMU consumers arm64: dts: renesas: r8a779h0: Add IPMMU nodes arm64: dts: renesas: r8a779h0: Add INTC-EX node arm64: dts: renesas: r8a779h0: Add MSIOF nodes arm64: dts: renesas: rzg3s-smarc-som: Enable eMMC by default riscv: dts: renesas: rzfive-smarc-som: Drop deleting interrupt properties from ETH0/1 nodes arm64: dts: renesas: r9a07g043: Move interrupt-parent property to common DTSI riscv: dts: renesas: r9a07g043f: Add IRQC node to RZ/Five SoC DTSI arm64: dts: renesas: s4sk: Fix ethernet0 alias Link: https://lore.kernel.org/r/cover.1714116737.git.geert+renesas@glider.beSigned-off-by:
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Arnd Bergmann authored
Merge tag 'v6.10-rockchip-dts64-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into soc/dt New boards: ArmSom Sige7, GameForce Chi,Forlinx FET3588-C with OK3588-C baseboard, Protonic MECSBC, Wolfvision PF5. The panthor driver for Mali Valhall GPUs landed, so a number of boards enable their gpu (Cool Pi, Theobroma-Systems boards, QuartzPro64, Rock5b, EVB1) Also the USBDP phy driver landed, allowing the usb3 dual-role controllers to be used on EVB1, Rock 5A and 5B, Indiedroid-Nova, Theobroma-Systems Tiger and Jaguar. A lot new peripherals for the Khadas Edge 2 (rtc, uart, sfc, adc, ir, usb, pcie, tf-card, pmic); PCIe3 support on Jaguar, audio support for the rk3308 and cache descriptions for rk356x and rk3328. Corrected model names for boards from Radxa, Pine64, Powkiddy, Anberic and general more dt cleanups. * tag 'v6.10-rockchip-dts64-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: (64 commits) arm64: dts: rockchip: add dual-role usb3 hosts to rk3588 Tiger-Haikou arm64: dts: rockchip: add usb-id extcon on rk3588 tiger arm64: dts: rockchip: fix comment for upper usb3 port arm64: dts: rockchip: fix pcie-refclk frequency on rk3588 tiger arm64: dts: rockchip: correct gpio_pwrctrl1 typos on rk3588(s) boards arm64: dts: rockchip: Correct the model names for Pine64 boards dt-bindings: arm: rockchip: Correct the descriptions for Pine64 boards arm64: dts: rockchip: Add ArmSom Sige7 board dt-bindings: arm: rockchip: Add ArmSoM Sige7 dt-bindings: vendor-prefixes: add ArmSoM arm64: dts: rockchip: add PCIe3 support on rk3588-jaguar arm64: dts: rockchip: move uart2 pinmux to dtsi on rk3588-tiger arm64: dts: rockchip: Add USB-C Support for rk3588s-indiedroid-nova arm64: dts: rockchip: correct the model name for Radxa ROCK 3A dt-bindings: arm: rockchip: correct the model name for Radxa ROCK 3A arm64: dts: rockchip: Correct the model names for Radxa ROCK 5 boards dt-bindings: arm: rockchip: Correct the descriptions for Radxa boards arm64: dts: rockchip: add lower USB3 port to rock-5b arm64: dts: rockchip: add upper USB3 port to rock-5a arm64: dts: rockchip: add USB3 to rk3588-evb1 ... Link: https://lore.kernel.org/r/15361932.O9o76ZdvQC@philSigned-off-by:
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Arnd Bergmann authored
Merge tag 'stm32-dt-for-v6.10-1' of git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32 into soc/dt STM32 DT for v6.10, round 1 Highlights: ---------- - MPU: - STM32MP13: - Add and enable LTDC display (rocktech,rk043fn48h) on stm32mp135f-dk. - Add firewall bus based on ETZPC firewall controller. - Add PWR regulator support: Can be only used if the platform is set as "no-secure" (RCC_SECCFGR cleared) either use SCMI regulator. - STMP32MP15: - Add firewall bus based on ETZPC firewall controller. - Add heartbeat on stm32mp157c-ed1. - STM32MP25: - Add firewall bus based on RIFSC firewall controller. - Add clock support (RCC) based on SCMI clock protocol for root clocks. - Add all I2C instances and declare i2c2/i2c8 on stm32mp257f-ev1. - Add all SPI instances. and declare spi3/spi8 on stm32mp257f-ev1. * tag 'stm32-dt-for-v6.10-1' of git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32: (21 commits) arm64: dts: st: correct masks for GIC PPI interrupts on stm32mp25 arm64: dts: st: add spi3 / spi8 properties on stm32mp257f-ev1 arm64: dts: st: add spi3/spi8 pins for stm32mp25 arm64: dts: st: add all 8 spi nodes on stm32mp251 arm64: dts: st: add i2c2 / i2c8 properties on stm32mp257f-ev1 arm64: dts: st: add i2c2/i2c8 pins for stm32mp25 arm64: dts: st: add all 8 i2c nodes on stm32mp251 arm64: dts: st: add rcc support for STM32MP25 ARM: dts: stm32: enable display support on stm32mp135f-dk board ARM: dts: stm32: add LTDC pinctrl on STM32MP13x SoC family ARM: dts: stm32: add LTDC support for STM32MP13x SoC family dt-bindings: display: simple: allow panel-common properties ARM: dts: stm32: add PWR regulators support on stm32mp131 media: dt-bindings: add access-controllers to STM32MP25 video codecs ARM: dts: stm32: add heartbeat led for stm32mp157c-ed1 ARM: dts: stm32: move can3 node from stm32f746 to stm32f769 ARM: dts: stm32: put ETZPC as an access controller for STM32MP13x boards ARM: dts: stm32: add ETZPC as a system bus for STM32MP13x boards ARM: dts: stm32: put ETZPC as an access controller for STM32MP15x boards ARM: dts: stm32: add ETZPC as a system bus for STM32MP15x boards ... Link: https://lore.kernel.org/r/2040767c-413e-4447-b354-c44999930e4c@foss.st.comSigned-off-by:
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https://github.com/hisilicon/linux-hisiArnd Bergmann authored
ARM64: DT: HiSilicon ARM64 DT updates for v6.10 - Move non-MMIO node out of soc for the hip05, hip06 and hip07 SoC - Miscellaneous fixes and improvements like correcting unit addresses and missing reg * tag 'hisi-arm64-dt-for-6.10' of https://github.com/hisilicon/linux-hisi: arm64: dts: hisilicon: hi6220: correct tsensor unit addresses arm64: dts: hisilicon: hi6220-hikey: drop unit addresses from fixed regulators arm64: dts: hisilicon: hi6220-hikey: add missing port@0 reg arm64: dts: hisilicon: hip07: correct unit addresses arm64: dts: hisilicon: hip07: move non-MMIO node out of soc arm64: dts: hisilicon: hip06: correct unit addresses arm64: dts: hisilicon: hip06: move non-MMIO node out of soc arm64: dts: hisilicon: hip05-d02: correct local-bus unit addresses arm64: dts: hisilicon: hip05: move non-MMIO node out of soc Link: https://lore.kernel.org/r/662A4115.9020805@hisilicon.comSigned-off-by:
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Arnd Bergmann authored
Merge tag 'samsung-dt64-6.10' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into soc/dt Samsung DTS ARM64 changes for v6.10 1. Add FIFO depth to each SPI node so we can avoid matching this through DTS alias. Difference SPI instances on given SoC have different FIFO depths. 2. Exynos850: add clock controllers providing clocks to CPUs. 3. Google GS101: few cleanups and add missing serial engine (USI) interface nodes. * tag 'samsung-dt64-6.10' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux: arm64: dts: exynos: gs101: define all PERIC USI nodes arm64: dts: exynos: gs101: join lines close to 80 chars arm64: dts: exynos: gs101: move pinctrl-* properties after clocks arm64: dts: exynos: gs101: move serial_0 pinctrl-0/names to dtsi arm64: dts: exynos: gs101: reorder pinctrl-* properties arm64: dts: exynos850: Add CPU clocks arm64: dts: exynosautov9: specify the SPI FIFO depth arm64: dts: exynos5433: specify the SPI FIFO depth Link: https://lore.kernel.org/r/20240425071856.9235-2-krzysztof.kozlowski@linaro.orgSigned-off-by:
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Arnd Bergmann authored
Merge tag 'samsung-dt-6.10' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into soc/dt Samsung DTS ARM changes for v6.10 1. Few cleanups of deprecated properties and node names pointed out by bindings newly converted to DT schema. 2. Fix S5PV210 NAND node size-cells, pointed out by DT schema. 3. Add FIFO depth to each SPI node so we can avoid matching this through DTS alias. Difference SPI instances on given SoC have different FIFO depths. 4. Fix Exynos4212 Galaxy Tab3 usable memory, because stock bootloader is not telling us truth. * tag 'samsung-dt-6.10' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux: ARM: dts: exynos4212-tab3: limit usable memory range ARM: dts: samsung: s5pv210: specify the SPI FIFO depth ARM: dts: samsung: exynos5420: specify the SPI FIFO depth ARM: dts: samsung: exynos5250: specify the SPI FIFO depth ARM: dts: samsung: exynos4: specify the SPI FIFO depth ARM: dts: samsung: exynos3250: specify the SPI FIFO depth ARM: dts: samsung: s5pv210: correct onenand size-cells ARM: dts: samsung: s5pv210: align onenand node name with bindings ARM: dts: samsung: exynos5800-peach-pi: switch to undeprecated DP HPD GPIOs ARM: dts: samsung: smdk4412: align keypad node names with dtschema ARM: dts: samsung: smdk4412: fix keypad no-autorepeat ARM: dts: samsung: exynos4412-origen: fix keypad no-autorepeat ARM: dts: samsung: smdkv310: fix keypad no-autorepeat Link: https://lore.kernel.org/r/20240425071856.9235-1-krzysztof.kozlowski@linaro.orgSigned-off-by:
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Arnd Bergmann authored
Merge tag 'omap-for-v6.10/dt-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into soc/dt Devicetree changes for omaps for v6.10 Update n900 charge limit, and make use of the clksel binding for dra7 for the clksel clocks and other dpll output related clocks. * tag 'omap-for-v6.10/dt-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: ARM: dts: dra7: Use clksel binding for CTRL_CORE_SMA_SW_0 ARM: dts: dra7: Use clksel binding for CM_CLKSEL_DPLL_USB ARM: dts: dra7: Use clksel binding for CM_CLKSEL_DPLL_PER ARM: dts: dra7: Use clksel binding for CM_CLKSEL_ABE_PLL_SYS ARM: dts: dra7: Use clksel binding for CM_CLKSEL_CORE ARM: dts: dra7: Use clksel binding for CM_CLKSEL_DPLL_EVE ARM: dts: dra7: Use clksel binding for CM_CLKSEL_DPLL_GMAC ARM: dts: dra7: Use clksel binding for CM_CLKSEL_DPLL_DRR ARM: dts: dra7: Use clksel binding for CM_CLKSEL_DPLL_GPU ARM: dts: dra7: Use clksel binding for CM_CLKSEL_DPLL_IVA ARM: dts: dra7: Use clksel binding for CM_CLKSEL_DPLL_DSP ARM: dts: dra7: Use clksel binding for CM_CLKSEL_DPLL_CORE ARM: dts: n900: set charge current limit to 950mA Link: https://lore.kernel.org/r/pull-1714020191-304166@atomide.comSigned-off-by:
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Rob Herring authored
The "arm,armv8-pmuv3" compatible is intended only for s/w models. Primarily, it doesn't provide any detail on uarch specific events. There's still remaining cases for CPUs without any corresponding PMU definition and for big.LITTLE systems which only have a single PMU node (there should be one per core type). Signed-off-by:
Rob Herring (Arm) <robh@kernel.org> Reviewed-by:
AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by:
Jisheng Zhang <jszhang@kernel.org> Acked-by:
Sudeep Holla <sudeep.holla@arm.com> Acked-by:
Dinh Nguyen <dinguyen@kernel.org> Acked-by:
Heiko Stuebner <heiko@sntech.de> Acked-by:
Bjorn Andersson <andersson@kernel.org> Acked-by:
Florian Fainelli <florian.fainelli@broadcom.com> Acked-by:
Alim Akhtar <alim.akhtar@samsung.com> Acked-by:
Thierry Reding <treding@nvidia.com> Acked-by:
Shawn Guo <shawnguo@kernel.org> Link: https://lore.kernel.org/r/20240417203853.3212103-1-robh@kernel.orgSigned-off-by:
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Arnd Bergmann authored
Merge tag 'renesas-dts-for-v6.10-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into soc/dt Renesas DTS updates for v6.10 - Add HDMI capture support for the Function expansion board for the Eagle development board, - Add PMIC support for the RZ/G2UL SMARC EVK development board, - Add thermal, more serial ((H)SCIF), and timer (CMT and TMU) support for the R-Car V4M SoC, - Add Timer Unit (TMU) support for the R-Mobile APE6, R-Car Gen2, and RZ/G1 SoCs, - Miscellaneous fixes and improvements. * tag 'renesas-dts-for-v6.10-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel: arm64: dts: renesas: rzg3s-smarc-som: Fix Ethernet aliases arm64: dts: renesas: r8a779h0: Add TMU nodes arm64: dts: renesas: r8a779h0: Add CMT nodes arm64: dts: renesas: gray-hawk-single: Enable nfsroot ARM: dts: renesas: r9a06g032: Remove duplicate interrupt-parent arm64: dts: renesas: gray-hawk-single: Add second debug serial port arm64: dts: renesas: r8a779h0: Add SCIF nodes arm64: dts: renesas: r8a779h0: Add remaining HSCIF nodes ARM: dts: renesas: rcar-gen2: Add TMU nodes ARM: dts: renesas: rzg1: Add TMU nodes ARM: dts: renesas: r8a73a4: Add TMU nodes ARM: dts: renesas: r7s72100: Add interrupt-names to SCIF nodes arm64: dts: renesas: r8a779h0: Add thermal nodes arm64: dts: renesas: rzg2ul-smarc: Enable PMIC and built-in RTC, GPIO and ONKEY arm64: dts: renesas: eagle: Add capture overlay for Function expansion board Link: https://lore.kernel.org/r/cover.1712915536.git.geert+renesas@glider.beSigned-off-by:
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Arnd Bergmann authored
Merge tag 'renesas-dt-bindings-for-v6.10-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into soc/dt Renesas DT binding updates for v6.10 - Document support for the Renesas RZ/V2H(P) (R9A09G057) SoC variants. * tag 'renesas-dt-bindings-for-v6.10-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel: dt-bindings: arm: renesas: Document Renesas RZ/V2H(P) System Controller dt-bindings: soc: renesas: Document Renesas RZ/V2H(P) SoC variants Link: https://lore.kernel.org/r/cover.1712915534.git.geert+renesas@glider.beSigned-off-by:
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- 26 Apr, 2024 4 commits
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Chris Morgan authored
Add device node for the H616 Non Maskable Interrupt (NMI) controller. This controller is present on all H616 boards and derivatives such as the T507 and H700. Note that on the H616 no NMI pad is exposed. Reviewed-by:
Andre Przywara <andre.przywara@arm.com> Signed-off-by:
Chris Morgan <macromorgan@hotmail.com> Acked-by:
Jernej Skrabec <jernej.skrabec@gmail.com> Link: https://lore.kernel.org/r/20240418181615.1370179-3-macroalpha82@gmail.comSigned-off-by:
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Mohammad Shehar Yaar Tausif authored
Replace "gpio" suffix with "gpios" for tegra20-ac97 DTS as the "gpio" suffix is deprecated. Signed-off-by:
Mohammad Shehar Yaar Tausif <sheharyaar48@gmail.com> Reviewed-by:
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by:
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Thierry Reding authored
Tegra194 and later chips have a coherency fabric, so some devices can be marked as DMA coherent to avoid unnecessary cache maintenance. Reviewed-by:
Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by:
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Nicolas Chauvet authored
The same table as ram-code 0 operates correctly on ram-code 1 v2: rebase on current kernel Signed-off-by:
Nicolas Chauvet <kwizart@gmail.com> Signed-off-by:
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- 25 Apr, 2024 21 commits
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Patrick Delaunay authored
Using GIC_CPU_MASK_SIMPLE(x), x should reflect the number of CPUs. STM32MP251 is a single core Cortex A35, STM32MP253 is a dual core CA35. Fixes: 5d30d03a ("arm64: dts: st: introduce stm32mp25 SoCs family") Signed-off-by:
Patrick Delaunay <patrick.delaunay@foss.st.com> Signed-off-by:
Alexandre Torgue <alexandre.torgue@foss.st.com>
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Alain Volmat authored
Add properties for spi3 and spi8 available on the stm32mp257f-ev1. Both are kept disabled since only used via the gpio expansion connector. Signed-off-by:
Alain Volmat <alain.volmat@foss.st.com> Signed-off-by:
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Alain Volmat authored
Add the spi3 and spi8 pins used on STM32MP257F-EV1 board. Signed-off-by:
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Alain Volmat authored
Add the 8 nodes for all spi instances available on the stm32mp251. Signed-off-by:
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Alain Volmat authored
Add properties for i2c2 and i2c8 available on the stm32mp257f-ev1. i2c2 is enabled since several devices are attached to it while i2c8 is kept disabled since only used via the gpio expansion connector. Signed-off-by:
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Alain Volmat authored
Add the i2c2 and i2c8 pins used on STM32MP257F-EV1 board. Signed-off-by:
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Alain Volmat authored
Add the 8 nodes for all i2c instances available on the stm32mp251. Signed-off-by:
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Gabriel Fernandez authored
Add RCC support to manage clocks and resets on the STM32MP25. Signed-off-by:
Gabriel Fernandez <gabriel.fernandez@foss.st.com> Signed-off-by:
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Raphael Gallais-Pou authored
Link panel and display controller. Enable panel, backlight and display controller. Signed-off-by:
Raphael Gallais-Pou <raphael.gallais-pou@foss.st.com> Signed-off-by:
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Raphael Gallais-Pou authored
Adds LTDC pinctrl support and assigns dedicated GPIO pins. Signed-off-by:
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Raphael Gallais-Pou authored
STM32MP13x SoC family embeds a new version of LTDC (Liquid crystal display - Thin film transistor) Display Controller. It provides a parallel digital RGB (red, green, blue) and signals for horizontal, vertical synchronization, pixel clock and data enable as output to interface directly to a variety of LCD-TFT panels. Main features * 2 input layers blended together to compose the display * Cropping of layers from any input size and location * Multiple input pixel formats: – Predefined ARGB, with 7 formats: ARGB8888, ABGR8888, RGBA8888, BGRA8888, RGB565, BGR565, RGB888packed. – Flexible ARGB, allowing any width and location for A,R,G,B components. – Predefined YUV, with 3 formats: YUV422-1L (FourCC: YUYV, Interleaved), YUV420-2L (FourCC: NV12, semi planar), YUV420-3L (FourCC: Yxx, full planar) with some flexibility on the sequence of the component. * Color look-up table (CLUT) up to 256 colors (256x24 bits) per layer * Color transparency keying * Composition with flexible window position and size versus output display * Blending with flexible layer order and alpha value (per pixel or constant) * Background underlying color * Gamma with non-linear configurable table * Dithering for output with less bits per component (pseudo-random on 2 bits) * Polarity inversion for HSync, VSync, and DataEnable outputs * Output as RGB888 24 bpp or YUV422 16 bpp * Secure layer (using Layer2) capability, with grouped regs and additional interrupt set * Interrupts based on 7 different events * AXI master interface with long efficient bursts (64 or 128 bytes) Signed-off-by:Yannick Fertre <yannick.fertre@foss.st.com> Signed-off-by:
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Raphael Gallais-Pou authored
This device inherits properties from panel-common. Those should be allowed to use, instead of specifying properties to true for each specific use. Signed-off-by:
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Marek Vasut authored
This patch adds STM32 PWR regulators DT support on stm32mp131. This requires TFA to clear RCC_SECCFGR, is disabled by default and can only be enabled on board DT level. Signed-off-by:
Marek Vasut <marex@denx.de> Signed-off-by:
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Hugues Fruchet authored
access-controllers is an optional property that allows a peripheral to refer to one or more domain access controller(s). Signed-off-by:
Hugues Fruchet <hugues.fruchet@foss.st.com> Acked-by:
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Patrice Chotard authored
Add heartbeat led for stm32mp157c-ed1. Signed-off-by:
Patrice Chotard <patrice.chotard@foss.st.com> Signed-off-by:
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Dario Binacchi authored
According to documents [1], [2] and [3], we have 2 CAN devices on the stm32f746 platform and 3 on the stm32f769 platform. So let's move the can3 node from stm32f746.dtsi to stm32f769.dtsi. [1] https://www.st.com/en/microcontrollers-microprocessors/stm32f7-series.html [2] RM0385: STM32F75xxx and STM32F74xxx advanced Arm
® -based 32-bit MCUs [3] RM0410: STM32F76xxx and STM32F77xxx advanced Arm® -based 32-bit MCUs Fixes: df362914 ("ARM: dts: stm32: re-add CAN support on stm32f746") Signed-off-by:Dario Binacchi <dario.binacchi@amarulasolutions.com> Signed-off-by:
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Alexandre Torgue authored
Reference ETZPC as an access-control-provider. For more information on which peripheral is securable or supports MCU isolation, please read the STM32MP13 reference manual Signed-off-by:
Gatien Chevallier <gatien.chevallier@foss.st.com> Signed-off-by:
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Gatien Chevallier authored
ETZPC is a firewall controller. Put all peripherals filtered by the ETZPC as ETZPC subnodes and keep the "simple-bus" compatible for backward compatibility. Signed-off-by:
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Gatien Chevallier authored
Reference ETZPC as an access-control-provider. For more information on which peripheral is securable or supports MCU isolation, please read the STM32MP15 reference manual Signed-off-by:
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Gatien Chevallier authored
ETZPC is a firewall controller. Put all peripherals filtered by the ETZPC as ETZPC subnodes and keep the "simple-bus" compatible for backward compatibility. Signed-off-by:
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Gatien Chevallier authored
RIFSC is a firewall controller. Add "st,stm32mp25-rifsc" compatible and reference RIFSC as an access-control-provider. Keep "simple-bus" compatible backward compatibility. Signed-off-by:
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- 23 Apr, 2024 2 commits
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Heiko Stuebner authored
Apart from the host-only usb3 controller (host2) the rk3588 also provides two dual-role controllers. On the Tiger-Haikou combination these are connected to the lower usb3-host port in host-only mode and the micro-usb3 port for dual-role operation. Add the necessary controllers, phys to the Tiger-Haikou board and enable the usb-id extcon. Signed-off-by:
Heiko Stuebner <heiko.stuebner@cherry.de> Reviewed-by:
Quentin Schulz <quentin.schulz@theobroma-systems.com> Link: https://lore.kernel.org/r/20240422163951.2604273-4-heiko@sntech.deSigned-off-by:
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Heiko Stuebner authored
The Q7 standard specifies a usb-id pin on the connector to distiuish between host and device mode. Model this via the usb-id extcon binding. While the pin is part of the Q7 standard, so part of the module, the extcon stays disabled in the som dtsi and will only be enabled in a baseboard using it. Signed-off-by:
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