- 09 Feb, 2023 9 commits
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Arnd Bergmann authored
When CONFIG_DRM_AMD_DC_DCN is disabled, the is_frl member is not defined: drivers/gpu/drm/amd/amdgpu/../display/dc/link/link_validation.c: In function 'dp_active_dongle_validate_timing': drivers/gpu/drm/amd/amdgpu/../display/dc/link/link_validation.c:126:66: error: 'const struct dc_dsc_config' has no member named 'is_frl' 126 | if (timing->flags.DSC && !timing->dsc_cfg.is_frl) | ^ Use the same #ifdef as the other references to this. Fixes: 54618888 ("drm/amd/display: break down dc_link.c") Signed-off-by:Arnd Bergmann <arnd@arndb.de> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Tom Rix authored
smatch reports drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c:90:6: warning: symbol 'should_disable_otg' was not declared. Should it be static? should_disable_otg() is only used in dcn315_clk_mgr.c, so it should be static Signed-off-by:
Tom Rix <trix@redhat.com> Signed-off-by:
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Alex Deucher authored
Use fb_start/end for consistency with gmc code for non- XGMI systems, they are equivalent to vram_start/end. Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Acked-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
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Alex Deucher authored
Need to cover both FB and AGP apertures. v2: fix missed gfxhub_v3_0_3.c Fixes: c6eafee0 ("Revert "Revert "drm/amdgpu/gmc11: enable AGP aperture""") Reviewed-by:
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Hamza Mahfooz authored
As made mention of in commit 4ea7fc09 ("drm/amd/display: Do not program interrupt status on disabled crtc"), we shouldn't program disabled crtcs. So, filter out disabled crtcs in dm_set_vupdate_irq() and dm_set_vblank(). Reviewed-by:
Harry Wentland <harry.wentland@amd.com> Fixes: 589d2739 ("drm/amd/display: Use crtc enable/disable_vblank hooks") Fixes: d2574c33 ("drm/amd/display: In VRR mode, do DRM core vblank handling at end of vblank. (v2)") Signed-off-by:
Hamza Mahfooz <hamza.mahfooz@amd.com> Signed-off-by:
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Jane Jian authored
sriov does not need to init pptable from amdgpu driver we finish it from PF Signed-off-by:
Jane Jian <Jane.Jian@amd.com> Acked-by:
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JesseZhang authored
test ib function is not necessary on hw ring, so remove it. v2: squash in NULL check fix Signed-off-by:
JesseZhang <Jesse.Zhang@amd.com> Acked-by:
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Guilherme G. Piccoli authored
Currently amdgpu calls drm_sched_fini() from the fence driver sw fini routine - such function is expected to be called only after the respective init function - drm_sched_init() - was executed successfully. Happens that we faced a driver probe failure in the Steam Deck recently, and the function drm_sched_fini() was called even without its counter-part had been previously called, causing the following oops: amdgpu: probe of 0000:04:00.0 failed with error -110 BUG: kernel NULL pointer dereference, address: 0000000000000090 PGD 0 P4D 0 Oops: 0002 [#1] PREEMPT SMP NOPTI CPU: 0 PID: 609 Comm: systemd-udevd Not tainted 6.2.0-rc3-gpiccoli #338 Hardware name: Valve Jupiter/Jupiter, BIOS F7A0113 11/04/2022 RIP: 0010:drm_sched_fini+0x84/0xa0 [gpu_sched] [...] Call Trace: <TASK> amdgpu_fence_driver_sw_fini+0xc8/0xd0 [amdgpu] amdgpu_device_fini_sw+0x2b/0x3b0 [amdgpu] amdgpu_driver_release_kms+0x16/0x30 [amdgpu] devm_drm_dev_init_release+0x49/0x70 [...] To prevent that, check if the drm_sched was properly initialized for a given ring before calling its fini counter-part. Notice ideally we'd use sched.ready for that; such field is set as the latest thing on drm_sched_init(). But amdgpu seems to "override" the meaning of such field - in the above oops for example, it was a GFX ring causing the crash, and the sched.ready field was set to true in the ring init routine, regardless of the state of the DRM scheduler. Hence, we ended-up using sched.ops as per Christian's suggestion [0], and also removed the no_scheduler check [1]. [0] https://lore.kernel.org/amd-gfx/984ee981-2906-0eaf-ccec-9f80975cb136@amd.com/ [1] https://lore.kernel.org/amd-gfx/cd0e2994-f85f-d837-609f-7056d5fb7231@amd.com/ Fixes: 067f44c8 ("drm/amdgpu: avoid over-handle of fence driver fini in s3 test (v2)") Suggested-by:
Luben Tuikov <luben.tuikov@amd.com> Signed-off-by:
Guilherme G. Piccoli <gpiccoli@igalia.com> Signed-off-by:
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Alex Deucher authored
Move variable declarations to where they are used. Fixes a segfault on smu7 V0 structures where some tables don't exist. Cc: Evan Quan <evan.quan@amd.com> Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/2388 Fixes: b1a9557a ("drm/amd/pm: fulfill powerplay peak profiling mode shader/memory clock settings") Reviewed-by:
Evan Quan <evan.quan@amd.com> Signed-off-by:
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- 08 Feb, 2023 20 commits
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Friedrich Vock authored
The pid field corresponds to the result of gettid() in userspace. However, userspace cannot reliably attribute PTE events to processes with just the thread id. This patch allows userspace to easily attribute PTE update events to specific processes by comparing this field with the result of getpid(). For attributing events to specific threads, the thread id is also contained in the common fields of each trace event. Reviewed-by:
Friedrich Vock <friedrich.vock@gmx.de> Signed-off-by:
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Kent Russell authored
These can support unique_id, so create the sysfs file for them Signed-off-by:
Kent Russell <kent.russell@amd.com> Reviewed-by:
Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com> Reviewed-by:
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Evan Quan authored
This can suppress the warning caused by version mismatch. Signed-off-by:
Guchun Chen <guchun.chen@amd.com> Signed-off-by:
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Aric Cyr authored
This version brings along the following: - FW 0.0.153.0 - Code re-organize for dc_link.c - Bug fixes on rotation, DRR and more Acked-by:
Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by:
Aric Cyr <aric.cyr@amd.com> Signed-off-by:
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Jingwen Zhu authored
[Why] This is a workaround for an dcn3.15 hang that happens if otg dispclk is ramped while otg is on and stream enc is off. But this w/a should not trigger when we have a dig active. [How] Avoid disable otg when dig was disabled. [Note] Reapplying commit b07bb766 ("drm/amd/display: avoid disable otg when dig was disabled") which was incorrectly reverted. Reviewed-by:
Josip Pavic <Josip.Pavic@amd.com> Acked-by:
Jingwen Zhu <Jingwen.Zhu@amd.com> Signed-off-by:
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Evan Quan authored
This can suppress the warning caused by version mismatch. Signed-off-by:
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Evan Quan authored
Add missing GetPptLimit message mapping. Signed-off-by:
Feifei Xu <Feifei.Xu@amd.com> Signed-off-by:
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Arnd Bergmann authored
A conversion from 'bool' to 'enum odm_combine_mode' was incomplete, and gcc warns about this with many instances of display/dc/dml/dcn20/display_mode_vba_20.c:3899:44: warning: implicit conversion from 'enum <anonymous>' to 'enum odm_combine_mode' [-Wenum-conversion] 3899 | locals->ODMCombineEnablePerState[i][k] = false; Change the ones that we get a warning for, using the same numerical values to leave the behavior unchanged. Fixes: 5fc11598 ("drm/amd/display: expand dml structs") Link: https://lore.kernel.org/all/20201026210039.3884312-3-arnd@kernel.org/ Link: https://lore.kernel.org/all/20210927100659.1431744-1-arnd@kernel.org/Signed-off-by:
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Randy Dunlap authored
The path for the "mod_info_packet.h" header file is incomplete, so add its location to the header search path in the amdgpu Makefile. See on ARCH=alpha (275 times in one build). In file included from ../drivers/gpu/drm/amd/amdgpu/amdgpu.h:90, from ../drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c:43: ../drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.h:62:10: fatal error: mod_info_packet.h: No such file or directory 62 | #include "mod_info_packet.h" | ^~~~~~~~~~~~~~~~~~~ compilation terminated. Fixes: 5b49da02 ("drm/amd/display: Enable Freesync over PCon") Signed-off-by:Randy Dunlap <rdunlap@infradead.org> Cc: Signed-off-by: Sung Joon Kim <sungkim@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: Christian König <christian.koenig@amd.com> Cc: "Pan, Xinhui" <Xinhui.Pan@amd.com> Cc: amd-gfx@lists.freedesktop.org Cc: dri-devel@lists.freedesktop.org Signed-off-by:
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Kent Russell authored
This looks like a standard copy/paste mistake. Replace the incorrect serial_number references with product_name and product_model Signed-off-by:
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Melissa Wen authored
Cursor gets clipped off in the middle of the screen with hw rotation 180. Fix a miscalculation of cursor offset when it's placed near the edges in the pipe split case. Cursor bugs with hw rotation were reported on AMD issue tracker: https://gitlab.freedesktop.org/drm/amd/-/issues/2247 The issues on rotation 270 was fixed by: https://lore.kernel.org/amd-gfx/20221118125935.4013669-22-Brian.Chang@amd.com/ that partially addressed the rotation 180 too. So, this patch is the final bits for rotation 180. Reported-by:
Xaver Hugl <xaver.hugl@gmail.com> Reviewed-by:
Melissa Wen <mwen@igalia.com> Signed-off-by:
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Anthony Koo authored
[Why&How] - Reduce reserved size from 9 to 8 dwords to reduce structure size and allow the union dmub_rb_cmd to fit into max 64-bytes cmd size Reviewed-by:
Anthony Koo <Anthony.Koo@amd.com> Signed-off-by:
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Hans de Goede authored
Remove CONFI_BACKLIGHT_CLASS_DEVICE ifdef that was accidently introduced back. Reviewed-by:
Hans de Goede <hdegoede@redhat.com> Signed-off-by:
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Wenjing Liu authored
[why] dc_link contains over 30k line of code, the decision is to break it down to files residing in link folder based on functionality. This change is the last break down change which will remove dc_link.c file after everything is broken down. [how] Move remaining dc_link.c functions into link_detection, link_dpms, link_validation, link_resource, and link_fpga and remove dc_link. Reviewed-by:
George Shen <George.Shen@amd.com> Acked-by:
Wenjing Liu <wenjing.liu@amd.com> Signed-off-by:
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Leo (Hanghong) Ma authored
[Why && How] Add support to read manufacturer OUI and device id from HDMI SCDC. Reviewed-by:
Leo (Hanghong) Ma <hanghong.ma@amd.com> Signed-off-by:
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Aurabindo Pillai authored
[Why&How] Fix the null pointer dererefence error when rotating the monitor on a DCN32 variant, which causes a call trace like: [ 42.469548] RIP: 0010:dcn20_program_front_end_for_ctx.cold+0x68/0x435 [amdgpu] [ 42.477140] Code: c1 4c 01 e8 48 8b b0 f0 01 00 00 e8 b6 1c 4c f9 42 f6 84 2b a0 0a 00 00 02 74 30 4d 03 ac 24 68 04 00 00 49 8b 85 f0 01 00 00 <83> b8 50 06 00 00 02 75 18 49 8b bd e0 02 00 00 48 8b 07 48 8b 40 [ 42.496225] RSP: 0018:ffffaf744326f6a0 EFLAGS: 00010282 [ 42.501539] RAX: 0000000000000000 RBX: ffff948765180000 RCX: 0000000000000000 [ 42.508797] RDX: 0000000000000000 RSI: ffffffffbaea5329 RDI: 00000000ffffffff [ 42.516055] RBP: ffff948701674400 R08: 0000000000000000 R09: ffffaf744326f538 [ 42.523312] R10: 0000000000000003 R11: ffff948a1d33ffe8 R12: ffff948708700000 [ 42.530569] R13: ffff94876e901180 R14: 0000000000000002 R15: 0000000000000001 [ 42.537825] FS: 00007f1c7c04a5c0(0000) GS:ffff948a05a80000(0000) knlGS:0000000000000000 [ 42.546055] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [ 42.551898] CR2: 0000000000000650 CR3: 0000000127dd6000 CR4: 00000000003506e0 [ 42.559155] Call Trace: [ 42.561645] <TASK> [ 42.563782] commit_planes_for_stream+0x8b1/0x1410 [amdgpu 2059945d14fb66c82032430b723fcb84d8250d46] [ 42.573298] dc_update_planes_and_stream+0x3f9/0x9f0 [amdgpu 2059945d14fb66c82032430b723fcb84d8250d46] [ 42.582986] amdgpu_dm_atomic_commit_tail+0x19be/0x3270 [amdgpu 2059945d14fb66c82032430b723fcb84d8250d46] [ 42.592944] ? vsnprintf+0x35e/0x550 [ 42.596593] commit_tail+0x94/0x130 [ 42.600146] drm_atomic_helper_commit+0x112/0x140 [ 42.604931] drm_atomic_commit+0x96/0xc0 [ 42.608922] ? drm_plane_get_damage_clips.cold+0x1c/0x1c [ 42.614326] drm_mode_atomic_ioctl+0x97b/0xb90 [ 42.618848] ? drm_atomic_set_property+0xb40/0xb40 [ 42.623633] drm_ioctl_kernel+0xc9/0x170 [ 42.627694] drm_ioctl+0x22f/0x410 [ 42.631157] ? drm_atomic_set_property+0xb40/0xb40 [ 42.636031] amdgpu_drm_ioctl+0x4a/0x80 [amdgpu 2059945d14fb66c82032430b723fcb84d8250d46] [ 42.644537] __x64_sys_ioctl+0x90/0xd0 [ 42.648355] do_syscall_64+0x5b/0x80 [ 42.651992] ? do_syscall_64+0x67/0x80 [ 42.655808] ? exit_to_user_mode_prepare+0x1e/0x140 [ 42.660773] entry_SYSCALL_64_after_hwframe+0x63/0xcd [ 42.665913] RIP: 0033:0x7f1c7f31aaff [ 42.669550] Code: 00 48 89 44 24 18 31 c0 48 8d 44 24 60 c7 04 24 10 00 00 00 48 89 44 24 08 48 8d 44 24 20 48 89 44 24 10 b8 10 00 00 00 0f 05 <41> 89 c0 3d 00 f0 ff ff 77 1f 48 8b 44 24 18 64 48 2b 04 25 28 00 [ 42.688635] RSP: 002b:00007fff29eca1a0 EFLAGS: 00000246 ORIG_RAX: 0000000000000010 [ 42.696334] RAX: ffffffffffffffda RBX: 00007fff29eca250 RCX: 00007f1c7f31aaff [ 42.703591] RDX: 00007fff29eca250 RSI: 00000000c03864bc RDI: 0000000000000009 [ 42.710848] RBP: 00000000c03864bc R08: 000000000000000e R09: 000000000000000e [ 42.718104] R10: 0000000000000007 R11: 0000000000000246 R12: 00005643f0991d70 [ 42.725361] R13: 0000000000000009 R14: 00005643f22d0c50 R15: 00005643f0a74550 [ 42.732621] </TASK> Reviewed-by:
Samson Tam <Samson.Tam@amd.com> Acked-by:
Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by:
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Wesley Chalmers authored
[WHY] DRR and Pipe cannot be updated on the same frame, or else underflow will occur. Reviewed-by:
Jun Lei <Jun.Lei@amd.com> Acked-by:
Wesley Chalmers <Wesley.Chalmers@amd.com> Signed-off-by:
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Wesley Chalmers authored
[WHY] Writing to DRR registers such as OTG_V_TOTAL_MIN on the same frame as a pipe commit can cause underflow. [HOW] Defer all DPP adjustment requests till optimized_required is false. Reviewed-by:
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Hamza Mahfooz authored
Currently, it is likely that we will read the relevant LTTPR caps after link training has completed (which can cause garbage data to be read), however according to the DP 2.0 spec that should be done before link training has commenced. So, instead of reading the registers on demand, use the values provided to us by DC. Reviewed-by:
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Kenneth Feng authored
enable athub cg on gc 11.0.3 Signed-off-by:
Kenneth Feng <kenneth.feng@amd.com> Reviewed-by:
Likun Gao <Likun.Gao@amd.com> Signed-off-by:
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- 03 Feb, 2023 11 commits
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Alex Deucher authored
This reverts commit 9aa15370. This is fixed now so we can re-enable S/G display on DCN 3.1.4. Reviewed-by:
Yifan Zhang <yifan1.zhang@amd.com> Signed-off-by:
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Alex Deucher authored
This reverts commit 1a65327a. This should be resolved so we can re-enable this. Also, the AGP apeture was bring programmed to 0 on MMHUB 3.0.1 since agp_start and end were not being set. Acked-by:
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Alex Deucher authored
Take into account whether or not the AGP aperture is enabled or not when calculating the system aperture. Fixes white screens with DCN 3.1.4. Based on a patch from Yifan Zhang <yifan1.zhang@amd.com> Cc: Yifan Zhang <yifan1.zhang@amd.com> Acked-by:
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Alex Deucher authored
Causes flickering or white screens in some configurations. Disable it for now until we can fix the issue. Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/2352 Cc: roman.li@amd.com Cc: yifan1.zhang@amd.com Reviewed-by:
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Alex Deucher authored
Causes flickering or white screens in some configurations. Disable it for now until we can fix the issue. Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/2352 Cc: roman.li@amd.com Cc: yifan1.zhang@amd.com Reviewed-by:
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Yifan Zha authored
[Why] Accessing GRBM_GFX_CNTL in full access time has risk when VF is doing MMIO attacking. Therefore, VF writing GRBM_GFX_CNTL are blocked by L1 Policy. For RLCG interface, RLCG use SCRATCH_REG2 which is copied from GRBM_GFX_CNTL. [How] Remove writing GRBM_GFX_CNTL in amdgpu_virt_rlcg_reg_rw. v2: Remove directly writing GRBM_GFX_INDEX in amdgpu_virt_rlcg_reg_rw as RLCG interface no need to use it. Signed-off-by:
Yifan Zha <Yifan.Zha@amd.com> Reviewed-by:
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Vitaly Prosyak authored
We allow sending PSP messages LOAD_ASD and UNLOAD_TA without acquiring a lock in drm_dev_enter during driver unload because we must call drm_dev_unplug as the beginning of unload driver sequence. Added WARNING if other PSP messages are sent without a lock. After this commit, the following commands would work -sudo modprobe -r amdgpu -sudo modprobe amdgpu Signed-off-by:
Vitaly Prosyak <vitaly.prosyak@amd.com> Reviewed-by Alex Deucher <alexander.deucher@amd.com> Signed-off-by:
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Guilherme G. Piccoli authored
This is a very trivial code clean-up related to commit 5468c36d ("drm/amd/display: Filter Invalid 420 Modes for HDMI TMDS"). This commit added a validation on driver probe to prevent invalid TMDS modes, but one of the fake properties (swizzle) ended-up causing a warning on driver probe; was reported here: https://gitlab.freedesktop.org/drm/amd/-/issues/2264. It was fixed by commit a1cbe691 ("drm/amd/display: patch cases with unknown plane state to prevent warning"), but the validation code had a double variable assignment, which we hereby remove. Also, the fix relies in the dcn2{0,1}patch_unknown_plane_state() callbacks, so while at it we took the opportunity to perform a small code clean-up in such routines. Cc: Aurabindo Pillai <aurabindo.pillai@amd.com> Cc: Daniel Wheeler <daniel.wheeler@amd.com> Cc: Fangzhi Zuo <Jerry.Zuo@amd.com> Cc: Harry Wentland <harry.wentland@amd.com> Cc: Leo Li <sunpeng.li@amd.com> Cc: Mark Broadworth <mark.broadworth@amd.com> Cc: Melissa Wen <mwen@igalia.com> Cc: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Cc: Sung Joon Kim <Sungjoon.Kim@amd.com> Cc: Swapnil Patel <Swapnil.Patel@amd.com> Reviewed-by:
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Tom Rix authored
cppcheck reports drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c:1403:76: style: Expression is always true because 'else if' condition is opposite to previous condition at line 1396. [multiCondition] } else if (context->res_ctx.pipe_ctx[i].stream->mall_stream_config.type == SUBVP_PHANTOM) { ^ drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c:1396:69: note: first condition if (context->res_ctx.pipe_ctx[i].stream->mall_stream_config.type != SUBVP_PHANTOM) { ^ drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c:1403:76: note: else if condition is opposite to first condition } else if (context->res_ctx.pipe_ctx[i].stream->mall_stream_config.type == SUBVP_PHANTOM) { It is not necessary to explicitly the check != condition, an else is simplier. Fixes: 238debca ("drm/amd/display: Use DML for MALL SS and Subvp allocation calculations") Signed-off-by: -
Tom Rix authored
checkpatch reports drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c:2902:13: style: Expression is always true because 'else if' condition is opposite to previous condition at line 2895. [multiCondition] } else if (blank) { ^ drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c:2895:6: note: first condition if (!blank) { ^ drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c:2902:13: note: else if condition is opposite to first condition } else if (blank) { It is not necessary to explicitly the check != condition, an else is simplier. Fixes: aa5a5777 ("drm/amd/display: Vari-bright looks disabled near end of MM14") Signed-off-by: -
ye xingchen authored
opp.h is included more than once. Signed-off-by:
ye xingchen <ye.xingchen@zte.com.cn> Signed-off-by:
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