- 04 Oct, 2018 8 commits
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Jeykumar Sankaran authored
This change gets rid of unwanted connector-encoder type mapping used for dsi-staging driver. Now that DPU will be using upstream DSI driver, remove the stale code. Signed-off-by:
Jeykumar Sankaran <jsanka@codeaurora.org> Signed-off-by:
Sean Paul <seanpaul@chromium.org> Signed-off-by:
Rob Clark <robdclark@gmail.com>
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Jeykumar Sankaran authored
Remove stale display port programming. It can be added back with DPU support for display port. Signed-off-by:
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Sravanthi Kollukuduru authored
The current driver has the opaque blend mode set as the default causing the black box effect around the cursor. The fix enables choosing a different blend mode for alpha enabled formats. Changes in V2: - Use drm_get_format_name() in the logs (Sean) Signed-off-by:
Sravanthi Kollukuduru <skolluku@codeaurora.org> Signed-off-by:
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Sravanthi Kollukuduru authored
Reserve DMA pipe for cursor plane and attach it to the crtc during the initialization. Changes in V2: None Signed-off-by:
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Stephen Boyd authored
We got a bug report that this function oopses when trying to do a kasprintf(). PC is at string+0x2c/0x60 LR is at vsnprintf+0x28c/0x4ec pc : [<ffffff80088d35d8>] lr : [<ffffff80088d5fc4>] pstate: a0c00049 sp : ffffff80095fb540 x29: ffffff80095fb540 x28: ffffff8008ad42bc x27: 00000000ffffffd8 x26: 0000000000000000 x25: ffffff8008c216c8 x24: 0000000000000000 x23: 0000000000000000 x22: ffffff80095fb720 x21: 0000000000000000 x20: ffffff80095fb720 x19: ffffff80095fb6f0 x18: 000000000000000a x17: 00000000b42ba473 x16: ffffff800805bbe8 x15: 00000000000a157d x14: 000000000000000c x13: 0000000000000000 x12: 0000ffff0000000f x11: 0000000000000003 x10: 0000000000000001 x9 : 0000000000000040 x8 : 000000000000001c x7 : ffffffffffffffff x6 : 0000000000000000 x5 : 0000000000000228 x4 : 0000000000000000 x3 : ffff0a00ffffff04 x2 : 0000000000007961 x1 : 0000000000000000 x0 : 0000000000000000 Process kworker/3:1 (pid: 61, stack limit = 0xffffff80095f8000) Call trace: Exception stack(0xffffff80095fb400 to 0xffffff80095fb540) b400: 0000000000000000 0000000000000000 0000000000007961 ffff0a00ffffff04 b420: 0000000000000000 0000000000000228 0000000000000000 ffffffffffffffff b440: 000000000000001c 0000000000000040 0000000000000001 0000000000000003 b460: 0000ffff0000000f 0000000000000000 000000000000000c 00000000000a157d b480: ffffff800805bbe8 00000000b42ba473 000000000000000a ffffff80095fb6f0 b4a0: ffffff80095fb720 0000000000000000 ffffff80095fb720 0000000000000000 b4c0: 0000000000000000 ffffff8008c216c8 0000000000000000 00000000ffffffd8 b4e0: ffffff8008ad42bc ffffff80095fb540 ffffff80088d5fc4 ffffff80095fb540 b500: ffffff80088d35d8 00000000a0c00049 ffffff80095fb550 ffffff80080d06a4 b520: ffffffffffffffff ffffff80088d5e0c ffffff80095fb540 ffffff80088d35d8 [<ffffff80088d35d8>] string+0x2c/0x60 [<ffffff80088d5fc4>] vsnprintf+0x28c/0x4ec [<ffffff80083973b8>] kvasprintf+0x68/0x100 [<ffffff800839755c>] kasprintf+0x60/0x80 [<ffffff800849cc24>] drm_encoder_init+0x134/0x164 [<ffffff80084d9a7c>] dpu_encoder_init+0x60/0x94 [<ffffff80084eced0>] _dpu_kms_drm_obj_init+0xa0/0x424 [<ffffff80084ed870>] dpu_kms_hw_init+0x61c/0x6bc [<ffffff80084f7614>] msm_drm_bind+0x380/0x67c [<ffffff80085114e4>] try_to_bring_up_master+0x228/0x264 [<ffffff80085116e8>] component_master_add_with_match+0x90/0xc0 [<ffffff80084f722c>] msm_pdev_probe+0x260/0x2c8 [<ffffff800851a910>] platform_drv_probe+0x58/0xa8 [<ffffff80085185c8>] driver_probe_device+0x2d8/0x40c [<ffffff8008518928>] __device_attach_driver+0xd4/0x10c [<ffffff800851644c>] bus_for_each_drv+0xb4/0xd0 [<ffffff8008518230>] __device_attach+0xd0/0x160 [<ffffff8008518984>] device_initial_probe+0x24/0x30 [<ffffff800851744c>] bus_probe_device+0x38/0x98 [<ffffff8008517aac>] deferred_probe_work_func+0x144/0x148 [<ffffff80080c8654>] process_one_work+0x218/0x3bc [<ffffff80080c883c>] process_scheduled_works+0x44/0x48 [<ffffff80080c95bc>] worker_thread+0x288/0x32c [<ffffff80080cea30>] kthread+0x134/0x13c [<ffffff8008084750>] ret_from_fork+0x10/0x18 Code: 910003fd 2a0403e6 eb0400ff 54000060 (38646845) Looking at the code I see that drm_encoder_init() is called from the DPU code with 'DRM_MODE_CONNECTOR_DSI' passed in as the 'encoder_type' argument (follow from _dpu_kms_initialize_dsi()). That corresponds to the integer 16. That is then indexed into drm_encoder_enum_list in drm_encoder_init() to look up the name of the encoder. If you're still following along, that's an encoder not a connector! We really want to use DRM_MODE_ENCODER_DSI (integer 6) instead of DRM_MODE_CONNECTOR_DSI here, or we'll go out of bounds of the encoder array. Pass the right thing and everything is fine. Cc: Jeykumar Sankaran <jsanka@codeaurora.org> Cc: Jordan Crouse <jcrouse@codeaurora.org> Cc: Sean Paul <seanpaul@chromium.org> Fixes: 25fdd593 (drm/msm: Add SDM845 DPU support) Tested-by:
Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org> Reviewed-by:
Stephen Boyd <swboyd@chromium.org> Signed-off-by:
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Sean Paul authored
If there is no bridge or panel connected to a dsi node, don't fail the entire msm bind. Just ignore the dsi block and move on. Cc: Doug Anderson <dianders@chromium.org> Reviewed-by:
Abhinav Kumar <abhinavk@codeaurora.org> Signed-off-by:
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Sean Paul authored
If dt parsing fails, we should return an error instead of pretending everything completed successfully. Cc: Doug Anderson <dianders@chromium.org> Reviewed-by:
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Sean Paul authored
Currently msm_dsi->id is initialized to 0 during kzalloc. If bind fails for a secondary dsi device before its id can be properly set (such as during dt parsing), the id will point to the primary dsi device, causing its reference to be removed from dsi_manager's global (msm_dsim_glb) array. This patch initializes the id to -1 and checks for negative in the manager cleanup. Cc: Doug Anderson <dianders@chromium.org> Reviewed-by:
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- 27 Sep, 2018 32 commits
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git://people.freedesktop.org/~agd5f/linuxDave Airlie authored
More new features and fixes for 4.20: - Add dynamic powergating support for VCN on picasso - Scheduler cleanup - Vega20 support for KFD - DC cleanups and bug fixes Signed-off-by:
Dave Airlie <airlied@redhat.com> From: Alex Deucher <alexdeucher@gmail.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180927184348.2696-1-alexander.deucher@amd.com
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git://anongit.freedesktop.org/tegra/linuxDave Airlie authored
drm/tegra: Changes for v4.20-rc1 This contains initial Tegra194 support as well as a couple of fixes for DMA/IOMMU integration. Signed-off-by:
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git://anongit.freedesktop.org/drm/drm-intelDave Airlie authored
Driver Changes: - Bugzilla 107600: Fix stuttering video playback on MythTV on old hardware (Chris) - Avoid black screen when using CSC coefficient matrix (Raviraj) - Hammer PDs on Baytrail to make sure they reload (Chris) - Capture some objects if unable to capture all, on error (Chris) - Add W/A for 16 GB DIMMs on SKL+ (Mahesh) - Only enable IPC for symmetric memory configurations on KBL+ (Mahesh) - Assume pipe A to have maximum stride limits (Ville) - Always update update OA contexts via context image (Tvrtko) - Icelake enabling patches (Madhav, Dhinakaran) - Add Icelake DMC firmware (Anusha) - Fixes for CI found corner cases (Chris) - Limit the backpressure for request allocation (Chris) - Park GPU on module load so usage starts from known state (Chris) - Flush tasklet when checking for idle (Chris) - Use coherent write into the context image on BSW+ (Chris) - Fix possible integer overflow for framebuffers that get aligned past 4GiB (Ville) - Downgrade fence timeout from warn to notice and add debug hint (Chris) - Fixes to multi function encoder code (Ville) - Fix sprite plane check logic (Dan, Ville) - PAGE_SIZE vs. I915_GTT_PAGE_SIZE fixes (Ville) - Decode memory bandwidth and parameters for BXT and SKL+ (Mahesh) - Overwrite BIOS set IPC value from KMS (Mahesh) - Multiple pipe handling code cleanups/restructurings/optimizations (Ville) - Spare low 4G address for non-48bit objects (Chris) - Free context_setparam of struct_mutex (Chris) - Delay updating ring register state on resume (Chris) - Avoid unnecessarily copying overlay IOCTL parameters (Chris) - Update GuC power domain states even without submission (Michal) - Restore GuC preempt-context across S3/S4 (Chris) - Add kernel selftest for rapid context switching (Chris) - Keep runtime power management ref for live selftests (Chris) - GEM code cleanups (Matt) Signed-off-by:
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git://anongit.freedesktop.org/drm/drm-miscDave Airlie authored
drm-misc-next for 4.20: UAPI Changes: - None Cross-subsystem Changes: - MAINTAINERS: Move udl, mxsfb, and fsl-dcu into drm-misc (Stefan, Sean) Core Changes: - syncobj: Check condition before returning timeout in schedule() (Chris) Driver Changes: - various: First wave of drm_fbdev_generic_setup() conversions (Noralf) - bochs/virtio: More format byte-order improvements (Gerd) - mxsfb: A couple fixes + add runtime pm support (Leonard) - virtio: Add vmap support for prime objects (Ezequiel) Cc: Stefan Agner <stefan@agner.ch> Cc: Sean Paul <sean@poorly.run> Cc: Noralf Trønnes <noralf@tronnes.org> Cc: Gerd Hoffman <kraxel@redhat.com> Cc: Leonard Crestez <leonard.crestez@nxp.com> Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Ezequiel Garcia <ezequiel@collabora.com> Signed-off-by:
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Nayan Deshmukh authored
having a delayed work item per job is redundant as we only need one per scheduler to track the time out the currently executing job. v2: the first element of the ring mirror list is the currently executing job so we don't need a additional variable for it v3: squash in fixes for v3d and etnaviv Signed-off-by:
Nayan Deshmukh <nayan26deshmukh@gmail.com> Suggested-by:
Christian König <christian.koenig@amd.com> Reviewed-by:
Alex Deucher <alexander.deucher@amd.com>
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Nathan Chancellor authored
Clang generates warnings when one enumerated type is implicitly converted to another. drivers/gpu/drm/amd/amdgpu/../powerplay/hwmgr/ppatomfwctrl.c:532:57: warning: implicit conversion from enumeration type 'enum atom_smu11_syspll0_clock_id' to different enumeration type 'BIOS_CLKID' (aka 'enum atom_smu9_syspll0_clock_id') [-Wenum-conversion] if (!pp_atomfwctrl_get_clk_information_by_clkid(hwmgr, SMU11_SYSPLL0_SOCCLK_ID, &frequency)) In this case, that is expected behavior. To make that clear to Clang without explicitly casting these values, change id's type to uint8_t in pp_atomfwctrl_get_clk_information_by_clkid so no conversion happens. Reported-by:Nick Desaulniers <ndesaulniers@google.com> Signed-off-by:
Nathan Chancellor <natechancellor@gmail.com> Signed-off-by:
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Shaoyun Liu authored
Firmware have the workaround to replace the atomic Ops with read-modify-write on CP side. User should not expect atomic Ops on system memory works normally if system didn't not support it. Signed-off-by:
Shaoyun Liu <Shaoyun.Liu@amd.com> Acked-by:
Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by:
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Jernej Skrabec authored
R40 DE2 mixers are similar to those found in A83T, except it needs different clock settings. Add a compatibles for them. Reviewed-by:
Chen-Yu Tsai <wens@csie.org> Acked-by:
Rob Herring <robh@kernel.org> Signed-off-by:
Jernej Skrabec <jernej.skrabec@siol.net> Signed-off-by:
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Chen-Yu Tsai authored
This reverts commit 3510e7a7. During the 4.19 merge window for drm-misc, two patches critical to supporting the display pipeline on the Allwinner R40 SoC were missed. They were applied later but missed the merge window deadline. As a result 4.19-rc1 kernel would crash on the R40 when it couldn't parse the new device tree structure. We ended up removing support for the R40 display pipeline for 4.19. Since the missing patches are already merged for 4.20, we can now revert the commit that removed support. Signed-off-by:
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Sean Paul authored
Backmerging 4.19-rc5 to pick up sun4i fix Signed-off-by: -
Alex Deucher authored
Fix some indentation issues. Reviewed-by:
James Zhu <James.Zhu@amd.com> Signed-off-by:
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Alex Deucher authored
expects argument of type ‘unsigned int’ has type ‘long int’ Fixes: 52e211c1 ("drm/amdgpu:Add error message when register failed to reach expected value") Reviewed-by:
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James Zhu authored
Add flag AMD_PG_SUPPORT_DPG to enable DPG mode on Picasso Signed-off-by:
Huang Rui <ray.huang@amd.com> Acked-by:
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James Zhu authored
Add functions to support VCN DPG pause mode. Signed-off-by:
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James Zhu authored
Add DPG pause state to support VCN DPG mode. Signed-off-by:
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James Zhu authored
Add DPG mode start/stop/mc_resume/clock_gating to support vcn 1.0 DPG mode. Signed-off-by:
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James Zhu authored
Some registers read/write needs program through SDRAM pool under DPG mode. Signed-off-by:
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James Zhu authored
Add DPG support flag for VCN DPG mode. Signed-off-by:
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James Zhu authored
New register offset/mask need to be added to support VCN DPG mode. Signed-off-by:
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James Zhu authored
Use register UVD_SCRATCH9 for VCN ring/ib test. Since those registers can't be directly accessed under DPG(Dynamic Power Gate) mode. Signed-off-by:
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Christian König authored
Everything that isn't related to the IH ring. Signed-off-by:
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Christian König authored
Add a callback to amdgpu_ih_process to remove most of the IV logic. Signed-off-by:
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Andrey Grodzovsky authored
Only print the warning if there was actually some fence processed from the SW fallback timer. v2: Add return value to amdgpu_fence_process to let amdgpu_fence_fallback know fences were actually processed and then print the warning. v3: Always return true if seq != last_seq Signed-off-by:
Andrey Grodzovsky <andrey.grodzovsky@amd.com> Reviewed-by:
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Christian König authored
Cleanup amdgpu_ih.c to be able to handle multiple interrupt rings. Signed-off-by:
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Christian König authored
We always want those to be setup correctly. Signed-off-by:
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Christian König authored
That is superflous here. Signed-off-by:
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Huang Rui authored
While the apg_end address is 0xffffffff, if add 1 with it, the value will be overflow and roll back to 0. So when 0 is written to mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR, the system aperture is actually disabled. And so any access to vram will trigger a page fault. Raven2's HW issue only need increase the vram end address, and needn't do it on the agp. Signed-off-by:
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Rex Zhu authored
Need to disable dpm features before halt rlc. Acked-by:
Rex Zhu <Rex.Zhu@amd.com> Signed-off-by:
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Rex Zhu authored
the CG related registers have been programed in golden setting PG register default value is 0. Acked-by:
Hang Zhou <hang.zhou@amd.com> Signed-off-by:
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Rex Zhu authored
before halt rlc/cp, need to 1. enter rlc safe mode 2. wait rlc/cp idle Acked-by:
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Rex Zhu authored
change function name gfx_v6/7/8/9_0_gpu_init to gfx_v6/7/8/9_0_constants_init. this function is just for init gfx constants such as max pipes, render backends... Reviewed-by:
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Andrey Grodzovsky authored
Deactivate SW interrupt fallback when all emited fences are completed. Also switch interrupt SW fallback message from INFO to WARN. v2: shorten the warning message a bit and only re-activate the timer during processing if it was already activated before. (Christian) Signed-off-by:
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