- 01 Jul, 2013 29 commits
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Florian Fainelli authored
BMIPS43xx CPUs have two hardware threads, and on some SoCs such as 3368, the bootloader has configured the system to boot from TP1 instead of the more usual TP0. Create the physical to logical CPU mapping to cope with that, do not remap the software interrupts to be cross CPUs such that we do not have to do use the logical CPU mapping further down the code, and finally, reset the slave TP1 only if booted from TP0. Signed-off-by:
Jonas Gorski <jogo@openwrt.org> Signed-off-by:
Florian Fainelli <florian@openwrt.org> Cc: linux-mips@linux-mips.org Cc: blogic@openwrt.org Cc: cernekee@gmail.com Patchwork: https://patchwork.linux-mips.org/patch/5553/ Patchwork: https://patchwork.linux-mips.org/patch/5556/Signed-off-by:
Ralf Baechle <ralf@linux-mips.org>
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David Daney authored
As Jonas Gorske said in his patch: Disable cpu_has_mmips for everything but SEAD3 and MALTA. Most of these platforms are from before the micromips introduction, so they are very unlikely to implement it. Reduces an -Os compiled, uncompressed kernel image by 8KiB for BCM63XX. This patch taks a different approach than his, we gate the runtime test for microMIPS by the config symbol SYS_SUPPORTS_MICROMIPS. Signed-off-by:
David Daney <david.daney@cavium.com> Cc: Jonas Gorski <jogo@openwrt.org> Cc: Steven J. Hill <Steven.Hill@imgtec.com> Acked-by:
Steven J. Hill <Steven.Hill@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5327/Signed-off-by:
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Tony Wu authored
There is an infinite loop in gic_set_affinity. When irq_set_affinity gets called on gic controller, it blocks forever. Signed-off-by:
Tony Wu <tung7970@gmail.com> Cc: Steven J. Hill <Steven.Hill@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5537/Signed-off-by:
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David Daney authored
The ABI allows these to be clobbered on syscalls, so only save and restore the multiplier state when the temporary registers need to be preserved. Signed-off-by:
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Aaro Koskinen authored
Enable interfaces on EdgeRouter Lite. Tested with cavium_octeon_defconfig and busybox shell. DHCP & ping works with eth0, eth1 and eth2. The board type "UBNT_E100" is taken from the sources of the vendor kernel shipped with the product. Signed-off-by:
Aaro Koskinen <aaro.koskinen@iki.fi> Acked-by:
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Jayachandran C authored
Prepare of a next patch which will call tlbmiss_handler_setup_pgd on microMIPS. MicroMIPS complains if the called code s not in the .text section. To fix this we generate code into space reserved in arch/mips/mm/tlb-funcs.S While there, move the rest of the generated functions (handle_tlbl, handle_tlbs, handle_tlbm) to the same file. Signed-off-by:
Jayachandran C <jchandra@broadcom.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5542/Signed-off-by:
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Ralf Baechle authored
MIPS I is the ancestor of all MIPS ISA and architecture variants. Anything ever build in the MIPS empire is either MIPS I or at least contains MIPS I. If it's running Linux, that is. So there is little point in having cpu_has_mips_1 because it will always evaluate as true - though usually only at runtime. Thus there is no point in having the MIPS_CPU_ISA_I ISA flag, so get rid of it. Little complication: traps.c was using a test for a pure MIPS I ISA as a test for an R3000-style cp0. To deal with that, use a check for cpu_has_3kex or cpu_has_4kex instead. cpu_has_3kex is a new macro. At the moment its default implementation is !cpu_has_4kex but this may eventually change if Linux is ever going to support the oddball MIPS processors R6000 and R8000 so users of either of these macros should not make any assumptions. Signed-off-by:
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Ralf Baechle authored
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Ralf Baechle authored
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Ralf Baechle authored
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David Daney authored
The serial port changes make it advisable to enable the proper UART drivers. Signed-off-by:
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David Daney authored
We will use 8250_dw instead. Signed-off-by:
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David Daney authored
A few differences needed by OCTEON: o These are DWC UARTS, but have USR at a different offset. o Internal SoC buses require reading back from registers to maintain write ordering. o 8250 on OCTEON appears with 64-bit wide registers, so when using readb/writeb in big endian mode we have to adjust the membase to hit the proper part of the register. o No UCV register, so we hard code some properties. Because OCTEON doesn't have a UCV register, I change where dw8250_setup_port(), which reads the UCV, is called by pushing it in to the OF and ACPI probe functions, and move unchanged dw8250_setup_port() earlier in the file. Signed-off-by:
Greg Kroah-Hartman <gregkh@linuxfoundation.org> Cc: Arnd Bergmann <arnd@arndb.de> Cc: Heikki Krogerus <heikki.krogerus@linux.intel.com> Cc: linux-mips@linux-mips.org Cc: Jamie Iles <jamie@jamieiles.com> Cc: Jiri Slaby <jslaby@suse.cz> Cc: linux-serial@vger.kernel.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/5516/Acked-by:
Arnd Bergmann <arnd@arndb.de> Reviewed-by:
Heikki Krogerus <heikki.krogerus@linux.intel.com> Signed-off-by:
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David Daney authored
Following patch to use generic 8250 drivers will need proper clock information. So when using the internal device tree, populate the "clock-frequency" property with the correct value. Signed-off-by:
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Florian Fainelli authored
Add support for the Netgear CVG834G and enable the two UARTs, Ethernet on the first MAC, PCI and the two leds. Signed-off-by:
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Florian Fainelli authored
Some boards may need to reset their external PHY or switch they are attached to, add a hook for doing this along with providing custom linux/gpio.h flags for doing this. Signed-off-by:
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Florian Fainelli authored
The BCM3368 SoC uses a NVRAM format which is not compatible with the one used by CFE, provide a default MAC address which is suitable for use and which is the default one also being used by the bootloader on these chips. Signed-off-by:
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Florian Fainelli authored
Add the firmware header format which is used by Broadcom Cable Modem SoCs such as the BCM3368 SoC. We export the bcm_hcs firmware format structure because it is used by user-land tools to create firmware images for these SoCs and will later be used by a corresponding MTD parser. Signed-off-by:
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Florian Fainelli authored
The Broadcom BCM3368 Cable Modem SoC is extremely similar to the existing BCM63xx DSL SoCs, in particular BCM6358, therefore little effort in the existing code base is required to get it supported. This patch adds support for the following on-chip peripherals: - two UARTS - GPIO - Ethernet - SPI - PCI - NOR Flash The most noticeable difference with 3368 is that it has its peripheral register at 0xfff8_0000 we check that separately in ioremap.h. Since 3368 is identical to 6358 for its clock and reset bits, we use them verbatim. Signed-off-by:
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Florian Fainelli authored
Enabling BOOT_RAW is mandatory to get a binary image (objcopy from ELF to binary) to work. This does not affect the ELF kernels which are used by CFE on BCM63XX DSL platforms, but is going to be necessary to support BCM63XX on Cable Modem chips such as BCM3368. Signed-off-by:
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Paul Gortmaker authored
This board has been EOL for many years now; lets not burden people doing build coverage and other tree wide work with working on essentially dead files. [ralf@linux-mips.org: Also remove arch/mips/include/asm/mach-wrppmc/war.h.] Signed-off-by:
Paul Gortmaker <paul.gortmaker@windriver.com> Cc: linux-mips@linux-mips.org Cc: Paul Gortmaker <paul.gortmaker@windriver.com> Patchwork: http://patchwork.linux-mips.org/patch/5503/Signed-off-by:
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Ralf Baechle authored
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Ralf Baechle authored
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Jonas Gorski authored
Commit 610019ba ("[MIPS] Remove unused function alloc_pci_controller.") removed the function, but left the prototype in the header file. Remove it as well so people don't get tempted to use it and wonder why it doesn't work. Signed-off-by:
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Jonas Gorski authored
All BCM63XX SoCs starting with BCM6358 have a BMIPS4350 instead of a BMIPS3300, so select it unless support for any of the older SoCs is selected. All BMIPS4350 have only two CPUs, so select the appropriate default. Signed-off-by:
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Kevin Cernekee authored
MIPS software IRQs 0 and 1 are used for interprocessor signaling (IPI) on BMIPS SMP. Make the board support code aware of them. Signed-off-by:
Kevin Cernekee <cernekee@gmail.com> [jogo@openwrt.org: move sw irqs behind timer irq] Signed-off-by:
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Gregory Fong authored
For non-SMP, uses the new random canary value that is stored in the task struct whenever a new task is forked. Based on ARM version in df0698be and subject to the same limitations: the variable GCC expects, __stack_chk_guard, is global, so this will not work on SMP. Quoting Nicolas Pitre <nico@fluxnic.net>: "One way to overcome this GCC limitation would be to locate the __stack_chk_guard variable into a memory page of its own for each CPU, and then use TLB locking to have each CPU see its own page at the same virtual address for each of them." Signed-off-by:
Gregory Fong <gregory.0xf0@gmail.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5488/Signed-off-by:
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Gregory Fong authored
Implements basic stack protector support based on ARM version in c743f380 , with Kconfig option, constant canary value set at boot time, and script to check if compiler actually supports stack protector. Tested by creating a kernel module that writes past end of char[]. Signed-off-by:
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Markos Chandras authored
When building with -fstack-protector, gcc emits the __stack_chk_guard and __stack_chk_fail symbols to check for stack stability. These symbols are defined in vmlinux but the generated vmlinux.bin that is used to create the compressed vmlinuz image has no symbol table so the linker can't find these symbols during the final linking phase. As a result of which, we need either to redefine these symbols just for the compressed image or drop the -fstack-protector option when building the compressed image. This patch implements the latter of two options. Fixes the following linking problem: dbg.c:(.text+0x7c): undefined reference to `__stack_chk_guard' dbg.c:(.text+0x80): undefined reference to `__stack_chk_guard' dbg.c:(.text+0xd4): undefined reference to `__stack_chk_guard' dbg.c:(.text+0xec): undefined reference to `__stack_chk_fail' [ralf@linux-mips.org: I'm applying this before the patch that actually adds stack protector support for MIPS. This means, it will not be possible to trigger above error message with any commit from the tree but rather they are what one would hit without this commit.] Signed-off-by:
Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Cc: Markos Chandras <markos.chandras@imgtec.com> Patchwork: https://patchwork.linux-mips.org/patch/5575/Signed-off-by:
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- 17 Jun, 2013 4 commits
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Grant Likely authored
The MIPS interrupt controllers are all registering their own irq_domains now. Drop the MIPS specific code because it is no longer needed. Signed-off-by:
Grant Likely <grant.likely@linaro.org> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/5458/Signed-off-by:
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Joe Perches authored
This typedef is unnecessary and should just be removed. Signed-off-by:
Joe Perches <joe@perches.com> Cc: Jiri Kosina <trivial@kernel.org> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/5460/Signed-off-by:
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Paul Bolle authored
The PMC MSP71XX gpio drivers were added in v2.6.28, see commit 9fa32c6b ("MIPS: PMC MSP71XX gpio drivers"). They are only built if CONFIG_HAVE_GPIO_LIB is set. But the Kconfig symbol HAVE_GPIO_LIB was already removed in v2.6.27, see commit 7444a72e ("gpiolib: allow user-selection"). So these drivers were never buildable. Perhaps no-one noticed because there are no in tree users of msp71xx_init_gpio() and msp71xx_init_gpio_extended(). Anyhow, these drivers can safely be removed. Signed-off-by:
Paul Bolle <pebolle@tiscali.nl> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/5345/Signed-off-by:
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Paul Bolle authored
promcon.o is built if CONFIG_PROM_CONSOLE is set. But there's no Kconfig symbol PROM_CONSOLE, so promcon.c is unbuildable. Remove it. Signed-off-by:
Maciej W. Rozycki <macro@linux-mips.org> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/5344/Signed-off-by:
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- 13 Jun, 2013 7 commits
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Jayachandran C authored
The invalid value for scratch register is -1, so update the checks of the form (scratch_reg > 0) to be (scratch_reg >= 0). This will fix the case in Netlogic XLP where the scratch_reg can be 0. Signed-off-by:
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Jayachandran C authored
XLR/XLP COP0 scratch is register 22, sel 0-7. Add a function c0_kscratch() which returns the scratch register for the platform, and use the return value while generating TLB handlers. Setup kscratch_mask to 0xf for XLR/XLP since the config4 register does not exist. This allows the kernel to allocate scratch registers 0-3 if needed. Signed-off-by:
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Jayachandran C authored
Fix an issue in plat_irq_dispatch due to which it can call do_IRQ with a PIC irq that is not mapped. When a per-cpu interrupt and a PIC interrupt are both active, the check 'eirr & PERCPU_IRQ_MASK' will be true, but the interrupt in 'i' will be the number of the PIC interrupt. In this case, we will call do_IRQ on the PIC interrupt without mapping it with nlm_irq_to_xirq(). Fix this by using __ffs64 instead of __ilog2_u64 and using the interrupt number instead of mask to identify per-cpu interrupts. Signed-off-by:
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Jayachandran C authored
The XLPs in production do not need these workarounds. Remove the code and the associated ifdef. Signed-off-by:
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Jayachandran C authored
Fix a cache error found in stress test, caused by the prefetch instruction going beyond valid memory when acessing the last page of a region. Add the pref_backup logic similar to XLR in XLP too. Signed-off-by:
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Jayachandran C authored
Earlier we just waited for the first thread of the CPU to come online before proceeding to wake up others. Update it to wait for all the CPUs in the core. This will be useful when the boot-up is slow, like while debugging or when running in a simulator. Signed-off-by:
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Jayachandran C authored
This does not cause a problem yet, but we do not want to write 1 to reserved bits. Signed-off-by:
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