Commits · 4e4101cfefd382176b05356c5ef112561ae10384 · Kirill Smelkov / linux

23 Oct, 2018 13 commits

riscv: Add support to no-FPU systems · 4e4101cf

Palmer Dabbelt authored Oct 22, 2018

This patchset adds an option, CONFIG_FPU, to enable/disable floating-
point support within the kernel.  The kernel's new behavior will be as
follows:

* with CONFIG_FPU=y
  All FPU codes are reserved.  If no FPU is found during booting, a
  global flag will be set, and those functions will be bypassed with
  condition check to that flag.

* with CONFIG_FPU=n
  No floating-point instructions in kernel and all related settings
  are excluded.
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>

4e4101cf

RISC-V: Cosmetic menuconfig changes · aef53f97

Nick Kossifidis authored Sep 20, 2018

* Move the built-in cmdline configuration on a new menu entry "Boot
  options", it doesn't make much sense to be part of the debuging menu.

* Rename "Kernel Type" menu to "Kernel features" to be more consistent with
  what other architectures are using, plus "type" is a bit misleading here.
Signed-off-by: Nick Kossifidis <mick@ics.forth.gr>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>

aef53f97

riscv: move GCC version check for ARCH_SUPPORTS_INT128 to Kconfig · ee592884

Masahiro Yamada authored Aug 24, 2018

This becomes much neater in Kconfig.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>

ee592884

RISC-V: remove the unused return_to_handler export · f31b8de9

Christoph Hellwig authored Sep 21, 2018

This export is not only not needed, but also breaks symbol versioning
due to being an undeclared assembly export.
Signed-off-by: Christoph Hellwig <hch@lst.de>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>

f31b8de9

RISC-V: Add futex support. · b90edb33

Jim Wilson authored Oct 16, 2018

Here is an attempt to add the missing futex support. I started with the MIPS
version of futex.h and modified it until I got it working. I tested it on
a HiFive Unleashed running Fedora Core 29 using the fc29 4.15 version of the
kernel. This was tested against the glibc testsuite, where it fixes 14 nptl
related testsuite failures. That unfortunately only tests the cmpxchg support,
so I also used the testcase at the end of

https://lwn.net/Articles/148830/

which tests the atomic_op functionality, except that it doesn't verify that
the operations are atomic, which they obviously are. This testcase runs
successfully with the patch and fails without it.

I'm not a kernel expert, so there could be details I got wrong here. I wasn't
sure about the memory model support, so I used aqrl which seemed safest, and
didn't add fences which seemed unnecessary. I'm not sure about the copyright
statements, I left in Ralf Baechle's line because I started with his code.
Checkpatch reports some style problems, but it is the same style as the MIPS
futex.h, and the uses of ENOSYS appear correct even though it complains about
them. I don't know if any of that matters.

This patch was tested on qemu with the glibc nptl/tst-cond-except
testcase, and the wake_op testcase from above.
Signed-off-by: Jim Wilson <jimw@sifive.com>
Reviewed-by: Christoph Hellwig <hch@lst.de>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>

b90edb33

RISC-V: Add FP register ptrace support for gdb. · b8c8a959

Jim Wilson authored Oct 17, 2018

Add a variable and a macro to describe FP registers, assuming only D is
supported.  FP code is conditional on CONFIG_FPU.  The FP regs and FCSR
are copied separately to avoid copying struct padding.  Tested by hand and
with the gdb testsuite.
Signed-off-by: Jim Wilson <jimw@sifive.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>

b8c8a959

RISC-V: Mask out the F extension on systems without D · 86e581e3

Palmer Dabbelt authored Aug 27, 2018

The RISC-V Linux port doesn't support systems that have the F extension
but don't have the D extension -- we actually don't support systems
without D either, but Alan's patch set is rectifying that soon. For now
I think we can leave this in a semi-broken state and just wait for
Alan's patch set to get merged for proper non-FPU support -- the patch
set is starting to look good, so doing something in-between doesn't seem
like it's worth the work.

I don't think it's worth fretting about support for systems with F but
not D for now: our glibc ABIs are IMAC and IMAFDC so they probably won't
end up being popular. We can always extend this in the future.

CC: Alan Kao <alankao@andestech.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>

86e581e3

RISC-V: Don't set cacheinfo.{physical_line_partition,attributes} · 1760debb

Palmer Dabbelt authored Jul 24, 2018

These are just hard coded in the RISC-V port, which doesn't make any
sense.  We should probably be setting these from device tree entries
when they exist, but for now I think it's saner to just leave them all
as their default values.
Reviewed-by: Jeremy Linton <jeremy.linton@arm.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>