- 03 May, 2016 1 commit
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Stephen Boyd authored
Merge tag 'sunxi-clocks-for-4.7' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux into clk-next Pull Allwinner clock driver updates from Maxime Ripard: As usual, a bunch of clocks patches for 4.7, mostly fixes and cleanups, and display-related clocks. * tag 'sunxi-clocks-for-4.7' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux: clk: sunxi: Let divs clocks read the base factor clock name from devicetree clk: sunxi: Add TCON channel1 clock clk: sunxi: Add PLL3 clock dt-bindings: clk: sun5i: add DRAM gates compatible clk: sunxi: Use resource_size clk: sunxi: Add sun6i/8i display support clk: sunxi: mod1 clock should modify it's parent
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- 02 May, 2016 2 commits
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Stephen Boyd authored
Merge tag 'tegra-for-4.7-clk' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into clk-next Pull tegra clk driver changes from Thierry Reding: This set of changes contains a bunch of cleanups and minor fixes along with some new clocks, mainly on Tegra210, in preparation for supporting DisplayPort and HDMI 2.0. * tag 'tegra-for-4.7-clk' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: clk: tegra: dfll: Reformat CVB frequency table clk: tegra: dfll: Properly clean up on failure and removal clk: tegra: dfll: Make code more comprehensible clk: tegra: dfll: Reference CVB table instead of copying data clk: tegra: dfll: Update kerneldoc clk: tegra: Fix PLL_U post divider and initial rate on Tegra30 clk: tegra: Initialize PLL_C to sane rate on Tegra30 clk: tegra: Fix pllre Tegra210 and add pll_re_out1 clk: tegra: Add sor_safe clock clk: tegra: dpaux and dpaux1 are fixed factor clocks clk: tegra: Add dpaux1 clock clk: tegra: Use correct parent for dpaux clock clk: tegra: Add fixed factor peripheral clock type clk: tegra: Special-case mipi-cal parent on Tegra114 clk: tegra: Remove trailing blank line clk: tegra: Constify peripheral clock registers clk: tegra: Add interface to enable hardware control of SATA/XUSB PLLs
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Stephen Boyd authored
Merge tag 'v4.7-rockchip-clk3' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-next Pull rockchip clk updates from Heiko Stuebner: A spelling fix and a bunch of rk3399 clock fixes. * tag 'v4.7-rockchip-clk3' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: clk: rockchip: fix the rk3399 cifout clock clk: rockchip: drop unnecessary CLK_IGNORE_UNUSED flags from rk3399 clk: rockchip: add some frequencies on the rk3399 PLL table clk: rockchip: assign more necessary rk3399 clock ids clk: rockchip: export some necessary rk3399 clock ids clk: rockchip: rename rga clock-id on rk3399 clk: rockchip: add general gpu soft-reset on rk3399 clk: rockchip: fix the gate bit for i2c4 and i2c8 on rk3399 clk: rockchip: fix of spelling mistake on unsuccessful in pll clock type
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- 28 Apr, 2016 17 commits
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Thierry Reding authored
Increase the readability of the CVB frequency table by reformatting it a little. Signed-off-by:Thierry Reding <treding@nvidia.com>
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Thierry Reding authored
Upon failure to probe the DFLL, the OPP table will not be cleaned up properly. Fix this and while at it make sure the OPP table will also be cleared upon driver removal. Signed-off-by: -
Thierry Reding authored
Rename some variables and structure fields to make the code more comprehensible. Also change the prototype of internal functions to be more in line with the OPP core functions. Signed-off-by: -
Thierry Reding authored
Instead of copying parts of the CVB table into a separate structure, keep track of the selected CVB table and directly reference data from it. Signed-off-by: -
Thierry Reding authored
The kerneldoc for struct tegra_dfll_soc_data is stale. Update it to match the current structure definition. Signed-off-by: -
Lucas Stach authored
The post divider value in the frequency table is wrong as it would lead to the PLL producing an output rate of 960 MHz instead of the desired 480 MHz. This wasn't a problem as nothing used the table to actually initialize the PLL rate, but the bootloader configuration was used unaltered. If the bootloader does not set up the PLL it will fail to come when used under Linux. To fix this don't rely on the bootloader, but set the correct rate in the clock driver. Signed-off-by:
Lucas Stach <dev@lynxeye.de> Signed-off-by:
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Lucas Stach authored
If the bootloader does not touch PLL_C it will stay in its reset state, failing to lock when enabled. This leads to consumers of this clock to fail probing. Fix this by always programming the PLL with a sane rate, which allows it to lock, at startup. Signed-off-by:
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Rhyland Klein authored
Use a new Tegra210 version of the pll_register_pllre function to allow setting the proper settings for the m and n div fields. Additionally define PLL_RE_OUT1 on Tegra210. Signed-off-by:
Rhyland Klein <rklein@nvidia.com> [treding@nvidia.com: define PLLRE_OUT1 register offset] Signed-off-by:
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Thierry Reding authored
The sor_safe clock is a fixed factor (1:17) clock derived from pll_p. It has a gate bit in the peripheral clock registers. While the SOR is being powered up, sor_safe can be used as the source until the SOR brick can generate its own clock. Signed-off-by: -
Thierry Reding authored
The dpaux (on Tegra124 and Tegra210) and dpaux1 (on Tegra210) are fixed factor clocks (1:17) and derived from pll_p_out0 (pll_p). They also have a gate bit in the peripheral clock registers. Signed-off-by: -
Thierry Reding authored
This clock is of the same type as dpaux and is added to feed into the second DPAUX block used in conjunction with SOR1. Signed-off-by: -
Thierry Reding authored
The dpaux clock is derived from pll_p_out0 (pll_p), not clk_m. Signed-off-by: -
Thierry Reding authored
Some of the peripheral clocks on Tegra are derived from one of the top- level PLLs with a fixed factor. Support these clocks by implementing the ->enable() and ->disable() callbacks using the peripheral clock register banks and the ->recalc_rate() by dividing the parent rate by the fixed factor. Signed-off-by: -
Thierry Reding authored
Starting with Tegra124, the mipi-cal clock uses the 72 MHz clock as its source. On Tegra114 this clock's parent was clk_m, so it is the one-off chip. Signed-off-by: -
Thierry Reding authored
Trailing blank lines are undesirable (several tools, such as git, complain about them), so remove it. Signed-off-by: -
Thierry Reding authored
The peripheral clock registers are defined in static tables. These tables never need to be modified at runtime, so they can reside in read-only memory. Signed-off-by: -
Andrew Bresticker authored
On Tegra210, hardware control of the SATA and XUSB pad PLLs must be done during the UPHY enable sequence rather than the PLLE enable sequence. Export functions to do this so that hardware control can be enabled from the XUSB padctl driver. Signed-off-by:
Andrew Bresticker <abrestic@chromium.org> Signed-off-by:
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- 25 Apr, 2016 11 commits
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Xing Zheng authored
The cifout clock is incorrect due to the manual error, we need to fix it. Signed-off-by:
Xing Zheng <zhengxing@rock-chips.com> Signed-off-by:
Heiko Stuebner <heiko@sntech.de>
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Xing Zheng authored
We don't need to many clocks enable after startup, to reduce some power consumption. Signed-off-by:
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Xing Zheng authored
This patch add some necessary frequencies for the RK3399 clock. Signed-off-by:
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Xing Zheng authored
Assign newly added clock ids. Signed-off-by:
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Heiko Stuebner authored
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Xing Zheng authored
We export some clock IDs for the reference drivers need them. Signed-off-by:
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Xing Zheng authored
The rga clock supplying the working clock on the rk3399 is actually called rga-core in the manual. As the clock id has neither been assigned nor released with a full kernel release, we can still change the id to the more appropriate naming. Signed-off-by:
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Xing Zheng authored
Add the id for the general gpu soft-reset, that got documented only in newer TRM versions. Signed-off-by:
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Xing Zheng authored
The gate bits of the i2c4 and i2c8 are incorrect due to the manual error, we need to fix them. Signed-off-by:
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Jens Kuske authored
Currently, the sunxi clock driver gets the name for the base factor clock of divs clocks from the name field in factors_data. This prevents reusing of the factor clock for clocks with same properties, but different name. This commit makes the divs setup function try to get a name from clock-output-names in the devicetree. It also removes the name field where possible and merges the sun4i PLL5 and PLL6 clocks. [Andre: Make temporary name allocation dynamic.] Signed-off-by:
Jens Kuske <jenskuske@gmail.com> Signed-off-by:
Andre Przywara <andre.przywara@arm.com> Signed-off-by:
Maxime Ripard <maxime.ripard@free-electrons.com>
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Colin Ian King authored
fix spelling mistake, unsucessful -> unsuccessful Signed-off-by:
Colin Ian King <colin.king@canonical.com> Signed-off-by:
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- 21 Apr, 2016 9 commits
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Maxime Ripard authored
The TCON is a controller generating the timings to output videos signals, acting like both a CRTC and an encoder. It has two channels depending on the output, each channel being driven by its own clock (and own clock controller). Add a driver for the channel 1 clock. Signed-off-by:
Rob Herring <robh@kernel.org> Acked-by:
Stephen Boyd <sboyd@codeaurora.org>
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Maxime Ripard authored
The A10 SoCs and relatives have a PLL controller to drive the PLL3 and PLL7, clocked from a 3MHz oscillator, that drives the display related clocks (GPU, display engine, TCON, etc.) Add a driver for it. Acked-by:
Chen-Yu Tsai <wens@csie.org> Acked-by:
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Maxime Ripard authored
The Allwinner SoCs have a gate controller to gate the access to the DRAM clock to the some devices that need to access the DRAM directly (mostly display / image related IPs). Use a simple gates driver to support the one found in the A13 / R8 SoCs. Signed-off-by:
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Vaishali Thakkar authored
Use the function resource_size instaed of explicit computation. Problem found using Coccinelle. Signed-off-by:
Vaishali Thakkar <vaishali.thakkar@oracle.com> Acked-by:
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Jean-Francois Moine authored
Add the clock type which is used by the sun6i/8i families for video display. Signed-off-by:
Jean-Francois Moine <moinejf@free.fr> Acked-by:
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Andrea Venturi authored
add CLK_SET_RATE_PARENT to modify the rate on clk upstream Signed-off-by:
Marcus Cooper <codekipper@gmail.com> Signed-off-by:
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Stephen Boyd authored
* 'clk-hw-register' (early part): clk: fixed-rate: Add hw based registration APIs clk: gpio: Add hw based registration APIs clk: composite: Add hw based registration APIs clk: fractional-divider: Add hw based registration APIs clk: fixed-factor: Add hw based registration APIs clk: mux: Add hw based registration APIs clk: gate: Add hw based registration APIs clk: divider: Add hw based registration APIs clkdev: Add clk_hw based registration APIs clk: Add clk_hw OF clk providers clk: Add {devm_}clk_hw_{register,unregister}() APIs clkdev: Remove clk_register_clkdevs() -
Stephen Boyd authored
* clk-composite-unregister: clk: composite: Add unregister function
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Maxime Ripard authored
The composite clock didn't have any unregistration function, which forced us to use clk_unregister directly on it. While it was already not great from an API point of view, it also meant that we were leaking the clk_composite structure allocated in clk_register_composite. Add a clk_unregister_composite function to fix this. Signed-off-by:
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