- 08 May, 2024 28 commits
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Lin.Cao authored
In interrupt context, write dbg_ev_file will be run by work queue. It will cause write dbg_ev_file execution after debug_trap_disable, which will cause NULL pointer access. v2: cancel work "debug_event_workarea" before set dbg_ev_file as NULL. Signed-off-by:
Lin.Cao <lincao12@amd.com> Reviewed-by:
Jonathan Kim <jonathan.kim@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Ma Jun authored
Check the ring type value to fix the out-of-bounds write warning Signed-off-by:
Ma Jun <Jun.Ma2@amd.com> Suggested-by:
Christian König <christian.koenig@amd.com> Reviewed-by:
Tim Huang <Tim.Huang@amd.com> Signed-off-by:
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Lijo Lazar authored
Range of possible values of pdev_num is 0-63. Use int8_t as data type. That also fixes below warnings: >> drivers/gpu/drm/amd/amdxcp/amdgpu_xcp_drv.c:59:58: warning: '%d' >> directive output may be truncated writing between 1 and 11 bytes into >> a region of size 9 [-Wformat-truncation=] 59 | snprintf(dev_name, sizeof(dev_name), "amdgpu_xcp_%d", pdev_num); | ^~ drivers/gpu/drm/amd/amdxcp/amdgpu_xcp_drv.c:59:46: note: directive argument in the range [-2147483648, 63] 59 | snprintf(dev_name, sizeof(dev_name), "amdgpu_xcp_%d", pdev_num); | ^~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdxcp/amdgpu_xcp_drv.c:59:9: note: 'snprintf' output between 13 and 23 bytes into a destination of size 20 59 | snprintf(dev_name, sizeof(dev_name), "amdgpu_xcp_%d", pdev_num); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Fixes: 97d814fe ("drm/amd/amdxcp: Use unique name for partition dev") Signed-off-by:Lijo Lazar <lijo.lazar@amd.com> Reported-by:
kernel test robot <lkp@intel.com> Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
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Lijo Lazar authored
This reverts commit c37ce764. RCCL library is currently not treating spatial partitions differently, hence this change is causing issues. Revert temporarily till RCCL implementation is ready for spatial partitions. Signed-off-by:
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Ma Jun authored
Check the user input and phy_id value range to fix "Using uninitialized value phy_id" Signed-off-by:
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Ma Jun authored
Assign an default value to agc_btc_response in failed case Signed-off-by:
Yang Wang <kevinyang.wang@amd.com> Signed-off-by:
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Ma Jun authored
Check return value of smum_send_msg_to_smc to fix uninitialized variable varning Signed-off-by:
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Tim Huang authored
1. Fix a issue that using uninitialized mask to get the ultimate frequency. 2. Check return of smu_cmn_send_smc_msg_with_param to avoid using uninitialized variable residency. Signed-off-by:
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Jack Xiao authored
kiq ring test has overwitten ready flag, need disable after gfx hw init. Signed-off-by:
Jack Xiao <Jack.Xiao@amd.com> Acked-by:
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Lang Yu authored
Small APUs(i.e., consumer, embedded products) usually have a small carveout device memory which can't satisfy most compute workloads memory allocation requirements. We can't even run a Basic MNIST Example with a default 512MB carveout. https://github.com/pytorch/examples/tree/main/mnist. Error Log: "torch.cuda.OutOfMemoryError: HIP out of memory. Tried to allocate 84.00 MiB. GPU 0 has a total capacity of 512.00 MiB of which 0 bytes is free. Of the allocated memory 103.83 MiB is allocated by PyTorch, and 22.17 MiB is reserved by PyTorch but unallocated" Though we can change BIOS settings to enlarge carveout size, which is inflexible and may bring complaint. On the other hand, the memory resource can't be effectively used between host and device. The solution is MI300A approach, i.e., let VRAM allocations go to GTT. Then device and host can flexibly and effectively share memory resource. v2: Report local_mem_size_private as 0. (Felix) Signed-off-by:
Lang Yu <Lang.Yu@amd.com> Reviewed-by:
Felix Kuehling <felix.kuehling@amd.com> Signed-off-by:
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Sunil Khatri authored
add the registers of SE block of gfx for ip dump for gfx10 IP. Signed-off-by:
Sunil Khatri <sunil.khatri@amd.com> Reviewed-by:
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Sunil Khatri authored
add registers in the ip dump for CP headers in gfx10 Signed-off-by:
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Mario Limonciello authored
Limit the workaround introduced by commit 31729e8c ("drm/amd/pm: fixes a random hang in S4 for SMU v13.0.4/11") to only run in the s4 path. Cc: Tim Huang <Tim.Huang@amd.com> Fixes: 31729e8c ("drm/amd/pm: fixes a random hang in S4 for SMU v13.0.4/11") Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/3351Signed-off-by:
Mario Limonciello <mario.limonciello@amd.com> Acked-by:
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Aric Cyr authored
This version brings along following fixes: - Fix some problems reported by Coverity - Fix idle optimization checks for multi-display and dual eDP - Fix incorrect size calculation for loop - Fix DSC-re-computing - Add Replay capability and state in debugfs - Refactor DCCG into component folder - Refactor input mode programming for DIG FIFO - Reset DSC clock in post unlock update - Clean-up recout calculation for visual confirm - Enable urgent latency adjustments for DCN35 Acked-by:
Tom Chung <chiahsuan.chung@amd.com> Signed-off-by:
Aric Cyr <aric.cyr@amd.com> Tested-by:
Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by:
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Anthony Koo authored
- Implement command interface to query ABM SW algorithm and HW caps. This is primarily intended as a debugging interface - Add new definitions for max number of histogram bins and ABM curve segments available in hardware - Add structures to retrieve caps to describe ABM HW caps since not all ASICs have the same number of cure segments and bins Acked-by:
Anthony Koo <anthony.koo@amd.com> Tested-by:
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Wenjing Liu authored
[why] Switching between DSC clock or disable DSC block are not double buffered update. Corruption is observed if these updates happen before DSC double buffered disconnection. [how] Move DSC disable and refclk reset to post unlock update. Wait for DSC double buffered disconnection and all mpccs are disconnected before reset DSC clock. Reviewed-by:
Samson Tam <samson.tam@amd.com> Acked-by:
Wenjing Liu <wenjing.liu@amd.com> Tested-by:
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Alvin Lee authored
This reverts commit 3351c608 ("drm/amd/display: Only program P-State force if pipe config changed") Which causes regression. Reviewed-by:
Alvin Lee <alvin.lee2@amd.com> Tested-by:
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Agustin Gutierrez authored
[Why] Some older MST hubs do not report DPCD registers according to specification. [How] This change re-applies commit c5365554 ("drm/amd/display: dsc mst re-compute pbn for changes on hub"). With an additional check for these older MST devices. Reviewed-by:
Swapnil Patel <swapnil.patel@amd.com> Acked-by:
Agustin Gutierrez <agustin.gutierrez@amd.com> Tested-by:
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Nicholas Kazlauskas authored
[Why] Idle optimizations are blocked if there's more than one eDP connector on the board - blocking S0i3 and IPS2 for static screen. [How] Fix the checks to correctly detect number of active eDP. Also restrict the eDP support to panels that have correct feature support. Cc: Mario Limonciello <mario.limonciello@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org Reviewed-by:
Charlene Liu <charlene.liu@amd.com> Acked-by:
Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Tested-by:
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Dillon Varone authored
[WHY & HOW] Make enable and disable sequences symmetric. Reviewed-by:
Dillon Varone <dillon.varone@amd.com> Tested-by:
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Bhuvana Chandra Pinninti authored
[why] cleaning up the code refactor requires hubp to be in its own component. [how] move all files under newly created hubp folder and fixing the makefiles. Reviewed-by:
Martin Leung <martin.leung@amd.com> Acked-by:
Bhuvana Chandra Pinninti <bhuvanachandra.pinninti@amd.com> Tested-by:
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Samson Tam authored
[Why & How] Split into a separate adjust and calculate call so we can let the caller adjust recout Reviewed-by:
Jun Lei <jun.lei@amd.com> Acked-by:
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Agustin Gutierrez authored
[Why] This fixes a bug introduced by commit c5365554 ("drm/amd/display: dsc mst re-compute pbn for changes on hub"). The change caused light-up issues with a second display that required DSC on some MST docks. [How] Use Virtual DPCD for DSC caps in MST case. [Limitations] This change only affects MST DSC devices that follow specifications additional changes are required to check for old MST DSC devices such as ones which do not check for Virtual DPCD registers. Reviewed-by:
Hersen Wu <hersenxs.wu@amd.com> Acked-by:
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Nicholas Susanto authored
[Why] Underflow occurs when running Netflix in a 4k144 eDP + 4k60 HDMI FRL setup. It is caused by latency varying based on the DCFCLK/FCLK state. [How] Enable urgent latency adjustment and match the reference to existing ASIC that also see increased latency at low FCLK. Reviewed-by:
Nicholas Susanto <nicholas.susanto@amd.com> Tested-by:
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Dillon Varone authored
[WHY] Input mode for the DIG FIFO should be programmed as part of stream encoder setup. [HOW] Pre-calculate the pixels per cycle as part of the pixel clock params, and program as part of stream encoder setup. Reviewed-by:
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Sreeja Golui authored
[Why] Providing a mechanism to manipulate the pwm frequency on the individual GPUs and monitor the transition during the switch. [How] Added a variable in dc_debug_options data structure. Using this variable to call the newly added command on the firmware. Reviewed-by:
Harry Vanzylldejong <harry.vanzylldejong@amd.com> Acked-by:
Sreeja Golui <sreeja.golui@amd.com> Tested-by:
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Tom Chung authored
[Why & How] User can get the panel replay capability and state for debug. sudo cat /sys/kernel/debug/dri/0/eDP-1/replay_capability "Sink support: no" - if panel doesn't support Replay "Sink support: yes" - if panel supports Replay "Driver support: no\n" - if driver doesn't support Replay "Driver support: yes\n" - if driver supports Replay sudo cat /sys/kernel/debug/dri/0/eDP-1/replay_state It will return current panel replay state Reviewed-by:
Sun peng Li <sunpeng.li@amd.com> Acked-by:
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Xi Liu authored
[Why and how] Current 420 ODM combine will override debug settings. Add support if debug settings is set for 420 ODM combine. Reviewed-by:
Xi Liu <xi.liu@amd.com> Tested-by:
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- 03 May, 2024 3 commits
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Sunil Khatri authored
reg_count is not used and the register count is directly derived from the array size and hence removed. Signed-off-by:
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Alex Hung authored
This fixes 12 UNINIT issues reported by Coverity. Reviewed-by:
Alex Hung <alex.hung@amd.com> Signed-off-by:
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Alex Hung authored
[WHY & HOW] The assignment of disp_cfg_index_max is missed and should be assigned to __DML2_WRAPPER_MAX_STREAMS_PLANES__. Fixes: 55ec7679 ("drm/amd/display: Limit array index according to architecture") Reviewed-by:
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- 02 May, 2024 9 commits
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Asad Kamal authored
Validate tbo resource pointer, skip if NULL Signed-off-by:
Asad Kamal <asad.kamal@amd.com> Reviewed-by:
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Hersen Wu authored
[Why] Coverity reports OVERRUN warning. soc.num_states could be 40. But array range of bw_params->clk_table.entries is 8. [How] Assert if soc.num_states greater than 8. Reviewed-by:
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Hersen Wu authored
[Why] Coverity report LOCK_EVASION warning. Access acrtc->wb_pending without lock wb_conn->job_lock. [How] Lock wb_conn->job_lock before accessing acrtc->wb_pending. Reviewed-by:
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Hersen Wu authored
[Why] Coverity reports Memory - illegal accesses. [How] Skip inactive planes. Reviewed-by:
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Alex Hung authored
[WHY & HOW] Make sure vmid0p72_idx, vnom0p8_idx and vmax0p9_idx calculation will never overflow and exceess array size. This fixes 3 OVERRUN and 1 INTEGER_OVERFLOW issues reported by Coverity. Reviewed-by:
Harry Wentland <harry.wentland@amd.com> Acked-by:
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Alex Hung authored
[Why & How] dml_stream_idx will be -1 when it is not found. Check and skip in such a case as -1 is not a valid array index. This fixes a NEGATIVE_RETURNS issue reported by Coverity. Reviewed-by:
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Alex Hung authored
[Why] dc_clk_table->entries has size of MAX_NUM_DPM_LVL(=8), but the loop counter i can go up to DML_MAX_CLK_TABLE_SIZE(=20) - 1. [How] The loop should be min(DML_MAX_CLK_TABLE_SIZE, MAX_NUM_DPM_LVL) - 1 instead. This fixes 21 OVERRUN issues reported by Coverity. Reviewed-by:
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Hersen Wu authored
[Why] For addtion (uint8_t) variable + constant 1, coverity generates message below: Truncation due to cast operation on "cur_idx + 1" from 32 to 8 bits. Then Coverity assume result is 32 bits value be saved into 8 bits variable. When result is used as index to access array, Coverity suspects index invalid. [How] Change varaible type to uint32_t. Reviewed-by:
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Alex Hung authored
[WHY & HOW] ctx->architecture determine array sizes of ODMMode and DPPPerSurface arrays to __DML2_WRAPPER_MAX_STREAMS_PLANES__ or __DML_NUM_PLANES__, and these array index should be checked before used This fixes 2 OVERRUN issues reported by Coverity. Reviewed-by:
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