- 27 Mar, 2015 11 commits
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Ander Conselvan de Oliveira authored
Some of the crtc_compute_clock() still depended on encoder->new_crtc since they didn't use intel_pipe_will_have_type() and used an open coded version of that function instead. This patch replaces those with the appropriate code that checks the atomic state intead. Signed-off-by:
Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com> [danvet: Separate the if (!connector) continue to facility easier extraction of a loop iterator for all of these (there's lots more in i915 and atomic helpers).] Signed-off-by:
Daniel Vetter <daniel.vetter@ffwll.ch>
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Ander Conselvan de Oliveira authored
The function intel_dp_set_drrs_state() would decide which pipe to downclock based on the staged config for the given connector. However, the result of that function is immediate, and it uses input values from crtc->config, so it should be looking at the current crtc instead. Signed-off-by:
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Ander Conselvan de Oliveira authored
Pass a crtc_state to it and find whether the pipe has an encoder of a given type by looking at the drm_atomic_state the crtc_state points to. Until recently i9xx_get_refclk() used to be called indirectly from vlv_force_pll_on() with a dummy crtc_state. That dummy crtc state is not converted to be part of a full drm atomic state, so add a WARN in case someone decides to call that again with a such dummy state. This was removed in commit 9cbe40c1 Author: Vijay Purushothaman <vijay.a.purushothaman@linux.intel.com> Date: Thu Mar 5 19:33:08 2015 +0530 drm/i915: Update prop, int co-eff and gain threshold for CHV v2: Warn if there is no connectors for a given crtc. (Daniel) Replace comment i9xx_get_refclk() with a WARN_ON(). (Ander) Signed-off-by:
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Ander Conselvan de Oliveira authored
Follow up patches will convert some functions called from there to use the atomic state, instead of directly accessing the new or current config. This patch just changes the parameters, but shouldn't have any functional changes. Signed-off-by:
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Michel Thierry authored
Traces for page directories and tables allocation and map. v2: Removed references to teardown. v3: bitmap_scnprintf has been deprecated. v4: Replace bitmap_scnprintf with scnprintf correctly, and get right range lengths. (Mika) Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com> Signed-off-by:
Michel Thierry <michel.thierry@intel.com> Reviewed-by:
Mika Kuoppala <mika.kuoppala@intel.com> Signed-off-by:
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Michel Thierry authored
This patch continues on the idea from "Track GEN6 page table usage". From here on, in the steady state, PDEs are all pointing to the scratch page table (as recommended in the spec). When an object is allocated in the VA range, the code will determine if we need to allocate a page for the page table. Similarly when the object is destroyed, we will remove, and free the page table pointing the PDE back to the scratch page. Following patches will work to unify the code a bit as we bring in GEN8 support. GEN6 and GEN8 are different enough that I had a hard time to get to this point with as much common code as I do. The aliasing PPGTT must pre-allocate all of the page tables. There are a few reasons for this. Two trivial ones: aliasing ppgtt goes through the ggtt paths, so it's hard to maintain, we currently do not restore the default context (assuming the previous force reload is indeed necessary). Most importantly though, the only way (it seems from empirical evidence) to invalidate the CS TLBs on non-render ring is to either use ring sync (which requires actually stopping the rings in order to synchronize when the sync completes vs. where you are in execution), or to reload DCLV. Since without full PPGTT we do not ever reload the DCLV register, there is no good way to achieve this. The simplest solution is just to not support dynamic page table creation/destruction in the aliasing PPGTT. We could always reload DCLV, but this seems like quite a bit of excess overhead only to save at most 2MB-4k of memory for the aliasing PPGTT page tables. v2: Make the page table bitmap declared inside the function (Chris) Simplify the way scratching address space works. Move the alloc/teardown tracepoints up a level in the call stack so that both all implementations get the trace. v3: Updated trace event to spit out a name v4: Aliasing ppgtt is now initialized differently (in setup global gtt) v5: Rebase to latest code. Also removed unnecessary aliasing ppgtt check for trace, as it is no longer possible after the PPGTT cleanup patch series of a couple of months ago (Daniel). v6: Implement changes from code review (Daniel): - allocate/teardown_va_range calls added. - Add a scratch page allocation helper (only need the address). - Move trace events to a new patch. - Use updated mark_tlbs_dirty. - Moved pt preallocation for aliasing ppgtt into gen6_ppgtt_init. v7: teardown_va_range removed (Daniel). In init, gen6_ppgtt_clear_range call is only needed for aliasing ppgtt. v8: Rebase after s/page_tables/page_table/. v9: Remove unnecessary scratch flag in page_table struct, future patches can just compare against ppgtt->scratch_pt, and alloc_pt_scratch becomes redundant. Initialize scratch_pt and pt. (Mika) v10: Clean up aliasing ppgtt init error path and prevent leaking the ppgtt obj when init fails. (Mika) Updated commit author. (Daniel) Cc: Mika Kuoppala <mika.kuoppala@intel.com> Signed-off-by:Ben Widawsky <ben@bwidawsk.net> Signed-off-by: Michel Thierry <michel.thierry@intel.com> (v4+) Reviewed-by:
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Michel Thierry authored
We are already unmapping them in gen6_ppgtt_free. This function became redundant since commit 06fda602 ("drm/i915: Create page table allocators"). Cc: Mika Kuoppala <mika.kuoppala@intel.com> Signed-off-by:
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Michel Thierry authored
i915_dma_map_single relies on dma_mapping_error, which returns positive error codes. Found by static checker. Introduced by commit 678d96fb ("drm/i915: Track GEN6 page table usage"). v2: Return negative error code and renamed commit title. (Dan) v3: Missing reported-by tag (Daniel) Reported-by:
Dan Carpenter <dan.carpenter@oracle.com> Cc: Dan Carpenter <dan.carpenter@oracle.com> Cc: Mika Kuoppala <mika.kuoppala@intel.com> Cc: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by:
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Michel Thierry authored
Found by static analysis tool, this was harmless as the pt was not used out of scope though. Introduced by commit 678d96fb ("drm/i915: Track GEN6 page table usage"). Cc: Mika Kuoppala <mika.kuoppala@intel.com> Signed-off-by:
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Tommi Rantala authored
Fix definition of the DRM_IOCTL_I915_GET_SPRITE_COLORKEY ioctl, so that it is different from the DRM_IOCTL_I915_SET_SPRITE_COLORKEY ioctl. Note that this is just for accuracy, the ioctl implementation itself is totally unused and already ripped out. Signed-off-by:
Tommi Rantala <tt.rantala@gmail.com> [danvet: Add note that this is a dead ioctl.] Signed-off-by:
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Daniel Vetter authored
It's completely unused and Tommi noticed that the #define is borked since forever. I've done a git search in userspace and only found broken definitions and no users anywhere. Cc: Tommi Rantala <tt.rantala@gmail.com> Signed-off-by:Daniel Vetter <daniel.vetter@intel.com>
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- 26 Mar, 2015 20 commits
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Ander Conselvan de Oliveira authored
Move towards atomic by using the legacy modeset's drm_atomic_state instead. Signed-off-by:
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Ander Conselvan de Oliveira authored
Move towards atomic by using the legacy modeset's drm_atomic_state instead. Signed-off-by:
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Ander Conselvan de Oliveira authored
Instead of using connector->new_encoder, get the same information from the pipe_config, thus making the function ready for the atomic conversion. Signed-off-by:
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Ander Conselvan de Oliveira authored
Move towards atomic by using the legacy modeset's drm_atomic_state instead. Signed-off-by:
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Ander Conselvan de Oliveira authored
Move towards atomic by using the legacy modeset's drm_atomic_state instead. Signed-off-by:
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Ander Conselvan de Oliveira authored
Move towards atomic by using the legacy modeset's drm_atomic_state instead. Signed-off-by:
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Ander Conselvan de Oliveira authored
Move towards atomic by using the legacy modeset's drm_atomic_state instead. v2: Move call to drm_atomic_add_affected_connectors() to intel_modeset_compute_config(). (Daniel) Signed-off-by: -
Ander Conselvan de Oliveira authored
With this in place, we can start converting pieces of the modeset code to look at the connector atomic state instead of the staged config. v2: Handle the load detect staged config changes too. (Ander) Remove unnecessary blank line. (Daniel) Signed-off-by: -
Ander Conselvan de Oliveira authored
Keep that state updated so that we can write code that depends on it on the follow up patches. v2: Fix BUG due to stale connector_state->crtc value. (Chandra) v3: Update comment about dummy state connectors. (Chandra) Signed-off-by:
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Ander Conselvan de Oliveira authored
So that we can add connector states to the drm_atomic_state used in the legacy modeset. Signed-off-by:
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kbuild test robot authored
drivers/gpu/drm/i915/intel_pm.c:2913:4-5: Unneeded semicolon Removes unneeded semicolon. Generated by: scripts/coccinelle/misc/semicolon.cocci CC: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Signed-off-by:
Fengguang Wu <fengguang.wu@intel.com> Signed-off-by:
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Ander Conselvan de Oliveira authored
For consistency, allocate a new crtc_state for a crtc that is being disabled. Previously only the enabled value of the current state would change. v2: Rebase on v5 of previous patch. (Ander) Signed-off-by:
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Ander Conselvan de Oliveira authored
For the atomic conversion, the mode set paths need to be changed to rely on an atomic state instead of using the staged config. By using an atomic state for the legacy code, we will be able to convert the code base in small chunks. v2: Squash patch that adds stat argument to intel_set_mode(). (Ander) Make every caller of intel_set_mode() allocate state. (Daniel) Call drm_atomic_state_clear() in set config's error path. (Daniel) v3: Copy staged config to atomic state in force restore path. (Ander) v4: Don't update ->new_config for disabled pipes in __intel_set_mode(), since it is expected to be NULL in that case. (Ander) v5: Don't change return type of intel_modeset_pipe_config(). (Chandra) Signed-off-by: -
Ander Conselvan de Oliveira authored
For now this is not necessary since intel_set_mode() doesn't acquire any new locks. However, once that function is converted to atomic, that will change, since we'll pass an atomic state to it, and that needs to have the right acquire context set. Signed-off-by:
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Ander Conselvan de Oliveira authored
The pattern of getting the crtc state with drm_atomic_get_crtc_state() and then converting it to intel_crtc_state will repeat quite often in the following patches, so add a helper function to save some typing. v2: Fix upcasting so that crtc_state base field could be moved. (Daniel) Signed-off-by:
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Daniel Vetter authored
Currently we only set preserve_bios_swizzling when the initial fb is shared and totally miss the single-screen case. Fix this by consolidating all the logic for both cases. This seems to go back to when swizzle preservation was originally merged in commit d9ceb816 Author: Jesse Barnes <jbarnes@virtuousgeek.org> Date: Thu Oct 9 12:57:43 2014 -0700 drm/i915: preserve swizzle settings if necessary v4 Cc: Kristian Høgsberg <hoegsberg@gmail.com> Cc: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by:
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Daniel Vetter authored
In spirit with commit 5724dbd1 Author: Damien Lespiau <damien.lespiau@intel.com> Date: Tue Jan 20 12:51:52 2015 +0000 drm/i915: Rename plane_config to initial_plane_config to make it clear that this code is all special-purpose for the initial plane takeover. Cc: Damien Lespiau <damien.lespiau@intel.com> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Reviewed-by:
Damien Lespiau <damien.lespiau@intel.com> Signed-off-by:
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Rodrigo Vivi authored
psr.active is being unset out of the if so this here is useless and duplicated. Signed-off-by:
Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by:
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Daniel Vetter authored
This is a very similar bug in the load detect code fixed in commit 9128b040 Author: Daniel Vetter <daniel.vetter@ffwll.ch> Date: Tue Mar 3 17:31:21 2015 +0100 drm/i915: Fix modeset state confusion in the load detect code But this time around it was the initial fb code that forgot to update the plane->crtc pointer. Otherwise it's the exact same bug, with the exact same restrains (any set_config call/ioctl that doesn't disable the pipe papers over the bug for free, so fairly hard to hit in normal testing). So if you want the full explanation just go read that one over there - it's rather long ... Cc: Matt Roper <matthew.d.roper@intel.com> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Josh Boyer <jwboyer@fedoraproject.org> Cc: Jani Nikula <jani.nikula@linux.intel.com> Reported-and-tested-by:
Josh Boyer <jwboyer@fedoraproject.org> Signed-off-by:
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Rodrigo Vivi authored
This flag was being mostly used as a meta flag in some cases and not covering other cases. One of the risks is that it was masking some frontbuffer trackings without disabling PSR. So, better to kill this at once and avoid umbrella parameters. Signed-off-by:
Chris Wilson <chris@chris-wilson.co.uk> [danvet: Drop unused out: label to appease gcc.] Signed-off-by:
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- 25 Mar, 2015 3 commits
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Mika Kuoppala authored
The faulting virtual address is >32bits and has been moved to different registers. Add to error state and output upper register first, in the same line for easy reconstruction of the fault address. v2: correct gen masking (Michel) v3: s/TBL/TLB (Ville) Signed-off-by:
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Tvrtko Ursulin authored
It should have been negative since it is returned with ERR_PTR(). Introduced in new code commit: commit 50470bb0 Author: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Date: Mon Mar 23 11:10:36 2015 +0000 drm/i915/skl: Support secondary (rotated) frame buffer mapping Signed-off-by:
Tvrtko Ursulin <tvrtko.ursulin@intel.com> Reported-by:
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Jesse Barnes authored
Or users can just spam the log all they want. Issue introduced in commit 9a8f0a12 Author: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Date: Fri Feb 27 11:15:24 2015 +0000 drm/i915/skl: Allow Y (and Yf) frame buffer creation References: https://bugs.freedesktop.org/show_bug.cgi?id=89628Signed-off-by:
Jesse Barnes <jbarnes@virtuousgeek.org> Reviewed-by:
Jani Nikula <jani.nikula@intel.com> Signed-off-by:
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- 24 Mar, 2015 3 commits
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Ramalingam C authored
As part of allocation of the drm_i915_private variable, drrs capability enum is initialized to DRRS_NOT_SUPPORTED. Hence need not initialize at each connector init. Moreover initializing this enum at connector init will reset the successful DRRS initialization of previous connector, as we have the DRRS support for only one panel at a time. Signed-off-by:
Ramalingam C <ramalingam.c@intel.com> Reviewed-by:
Sivakumar Thulasimani <sivakumar.thulasimani@intel.com> Signed-off-by:
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Imre Deak authored
The logical place for clearing the RPS latched interrupt bits is when resetting the RPS interrupts, so move the corresponding part from the RPS disable function to the reset function. During resetting we already cleared the IIR bits, so the only thing missing there was clearing pm_iir. Note that we call gen6_disable_rps_interrupts() also during driver load and resume time via intel_uncore_sanitize() when i915 interrupts are still not installed. If there are any pending RPS bits at this point (which after this patch wouldn't be cleared) they will be cleared by the reset code via the interrupt preinstall hooks. Signed-off-by:
Imre Deak <imre.deak@intel.com> Signed-off-by:
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Imre Deak authored
When disabling RPS interrupts there is a race where we disable RPS inerrupts while the interrupt handler is running and the handler has already latched the pending RPS interrupt from the master IIR register. Afterwards the disabling path clears the PM IIR bits, making the state of pending interrupts inconsistent from the interrupt handler's point of view. This triggers the following warning: "The master control interrupt lied (PM)!". To fix this make sure that any running interrupt handler (which may have already latched the master IIR) finishes before clearing the IIR bits. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=87347Signed-off-by:
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- 23 Mar, 2015 3 commits
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Tvrtko Ursulin authored
v2: Pass in rotation info to sprite plane updates as well. v3: Use helper to determine 90/270 rotation. (Michel Thierry) v4: Rebased for fb modifiers and atomic changes. For: VIZ-4546 Signed-off-by:
Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Signed-off-by:
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Tvrtko Ursulin authored
Need to do this in order to support 90/270 rotated display. v2: Pass in drm_plane instead of plane index to intel_obj_display_address. v3: * Renamed intel_obj_display_address to intel_plane_obj_offset. (Chris Wilson) * Simplified rotation check to bitwise AND. (Chris Wilson) v4: * Extracted 90/270 rotation check into a helper function. (Michel Thierry) v5: * Rebased for ggtt view changes. For: VIZ-4545 Signed-off-by: -
Tvrtko Ursulin authored
90/270 rotated scanout needs a rotated GTT view of the framebuffer. This is put in a separate VMA with a dedicated ggtt view and wired such that it is created when a framebuffer is pinned to a 90/270 rotated plane. Rotation is only possible with Yb/Yf buffers and error is propagated to user space in case of a mismatch. Special rotated page view is constructed at the VMA creation time by borrowing the DMA addresses from obj->pages. v2: * Do not bother with pages for rotated sg list, just populate the DMA addresses. (Daniel Vetter) * Checkpatch cleanup. v3: * Rebased on top of new plane handling (create rotated mapping when setting the rotation property). * Unpin rotated VMA on unpinning from display plane. * Simplify rotation check using bitwise AND. (Chris Wilson) v4: * Fix unpinning of optional rotated mapping so it is really considered to be optional. v5: * Rebased for fb modifier changes. * Rebased for atomic commit. * Only pin needed view for display. (Ville Syrjälä, Daniel Vetter) v6: * Rebased after preparatory work has been extracted out. (Daniel Vetter) v7: * Slightly simplified tiling geometry calculation. * Moved rotated GGTT view implementation into i915_gem_gtt.c (Daniel Vetter) v8: * Do not use i915_gem_obj_size to get object size since that actually returns the size of an VMA which may not exist. * Rebased for ggtt view changes. v9: * Rebased after code review changes on the preceding patches. * Tidy function definitions. (Joonas Lahtinen) For: VIZ-4726 Signed-off-by:
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