- 14 Jun, 2024 40 commits
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Rodrigo Siqueira authored
Use dc_wake_and_execute_gpint with DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY to get the replay state. Signed-off-by:
Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Acked-by:
Zaeem Mohamed <zaeem.mohamed@amd.com> Tested-by:
Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Yang Wang authored
refine imu firmware loading Signed-off-by:
Yang Wang <kevinyang.wang@amd.com> Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
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Yang Wang authored
refine pmfw/smu firmware loading Signed-off-by:
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Yang Wang authored
refine gmc firmware loading Signed-off-by:
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Yang Wang authored
refine vpe firmware loading Signed-off-by:
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Yang Wang authored
refine vcn firmware loading Signed-off-by:
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Yang Wang authored
adjust the function position to better match aca/mca fini code in ras_fini(). Signed-off-by:
Tao Zhou <tao.zhou1@amd.com> Signed-off-by:
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Bob Zhou authored
To fix potential overflowed constant warning, modify the variables to u32 for getting the return value of RREG32_SOC15(). Signed-off-by:
Bob Zhou <bob.zhou@amd.com> Acked-by:
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Harish Kasiviswanathan authored
To achieve full occupancy CP hardware needs to know if CUs in SE are symmetrically or asymmetrically harvested v2: Reset is_symmetric_cus for each loop Signed-off-by:
Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com> Acked-by:
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Lijo Lazar authored
Skip scheduling coredump when gpu reset is intentionally triggered through debugfs. Signed-off-by:
Lijo Lazar <lijo.lazar@amd.com> Reviewed-by:
Asad Kamal <asad.kamal@amd.com> Reviewed-by:
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Yang Wang authored
refine sdma firmware loading Signed-off-by:
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Yang Wang authored
refine psp firmware loading Signed-off-by:
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Yunxiang Li authored
We need to take the reset domain lock before talking to MES. While in this case we can take the lock inside the mes helper. We can't do so for most other mes helpers since they are used during reset. So for consistency sake we add the lock here. Signed-off-by:
Yunxiang Li <Yunxiang.Li@amd.com> Reviewed-by:
Felix Kuehling <felix.kuehling@amd.com> Signed-off-by:
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Yang Wang authored
v1: refine mes firmware loading v2: use dev_info instead of DRM_INFO Signed-off-by:
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Mukul Joshi authored
Add missing locking at a few places when calling MES APIs to ensure exclusive access to MES queue. Signed-off-by:
Mukul Joshi <mukul.joshi@amd.com> Reviewed-by:
Kent Russell <kent.russell@amd.com> Signed-off-by:
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Mario Limonciello authored
Currently, amdgpu will always set up the brightness at 100% when it loads. However this is jarring when the BIOS has it previously programmed to a much lower value. The ACPI ATIF method includes two members for "ac_level" and "dc_level". These represent the default values that should be used if the system is brought up in AC and DC respectively. Use these values to set up the default brightness when the backlight device is registered. v2: squash in ACPI fix Reviewed-by:
Leo Li <sunpeng.li@amd.com> Acked-by:
Mario Limonciello <mario.limonciello@amd.com> Signed-off-by:
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David (Ming Qiang) Wu authored
Similar to commit 813e7d4c where some kernel log messages are dropped. With this commit, more log messages in older version of VCN/JPEG code are dropped. Acked-by:
Leo Liu <leo.liu@amd.com> Signed-off-by:
David (Ming Qiang) Wu <David.Wu3@amd.com> Signed-off-by:
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Ivan Lipski authored
Revert "drm/amd/display: Add NULL check for 'afb' before dereferencing in amdgpu_dm_plane_handle_cursor_update" [WHY] This patch is a dupplicate implementation of 14bcf29b, which we are reverting due to a regression with kms_plane_cursor IGT tests. This reverts commit 38e6f715. Reviewed-by:
Srinivasan Shanmugam <srinivasan.shanmugam@amd.com> Tested-by:
George Zhang <George.zhang@amd.com> Signed-off-by:
Ivan Lipski <ivlipski@amd.com> Signed-off-by:
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Ivan Lipski authored
[WHY] This commit introduced a regression with kms_plane_cursor IGT tests, causing AMD Asics to fail these tests. This reverts commit ce66ffd9. Reviewed-by:
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Yang Wang authored
refine gpu_info firmware loading Signed-off-by:
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Hamza Mahfooz authored
We can't read/write to DCN registers while in IPS. Since, that can cause the system to hang. So, before proceeding with the access in that scenario, force the system out of IPS. Cc: stable@vger.kernel.org # 6.6+ Reviewed-by:
Roman Li <roman.li@amd.com> Signed-off-by:
Hamza Mahfooz <hamza.mahfooz@amd.com> Signed-off-by:
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Yang Wang authored
v1: Adding formatting string feature to improve function flexibility. v2: modify macro name to ADMGPU_UCODE_MAX_NAME. Signed-off-by:
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Bob Zhou authored
To fix potential overflowed constant warning reported by Coverity, modify the variables to uint32_t. Signed-off-by:
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Yunxiang Li authored
We need to take the reset domain lock before flush hdp. We can't put the lock inside amdgpu_device_flush_hdp itself because it is used during reset where we already take the write side lock. Signed-off-by:
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Yunxiang Li authored
Which method is used to flush tlb does not depend on whether a reset is in progress or not. We should skip flush altogether if the GPU will get reset. So put both path under reset_domain read lock. Signed-off-by:
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Yunxiang Li authored
Here since we are in reset and takes the reset_domain write side lock already. We can't use the flush tlb helper which tries to take the read side. Signed-off-by:
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Yunxiang Li authored
When amdgpu_gart_invalidate_tlb helper is introduced this part was left out of the conversion. Avoid the code duplication here. Signed-off-by:
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Yunxiang Li authored
At this point the gart is not set up, there's no point to invalidate tlb here and it could even be harmful. Signed-off-by:
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Yunxiang Li authored
is_hws_hang and is_resetting serves pretty much the same purpose and they all duplicates the work of the reset_domain lock, just check that directly instead. This also eliminate a few bugs listed below and get rid of dqm->ops.pre_reset. kfd_hws_hang did not need to avoid scheduling another reset. If the on-going reset decided to skip GPU reset we have a bad time, otherwise the extra reset will get cancelled anyway. remove_queue_mes forgot to check is_resetting flag compared to the pre-MES path unmap_queue_cpsch, so it did not block hw access during reset correctly. Signed-off-by:
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Yunxiang Li authored
We send back the ready to reset message before we stop anything. This is wrong. Move it to when we are actually ready for the FLR to happen. In the current state since we take tens of seconds to stop everything, it is very likely that host would give up waiting and reset the GPU before we send ready, so it would be the same as before. But this gets rid of the hack with reset_domain locking and also let us tell how slow ready to reset actually is from the host. The ready to reset speed can be improved later. Signed-off-by:
Emily Deng <Emily.Deng@amd.com> Signed-off-by:
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Yunxiang Li authored
Accessing registers via host is missing the check for skip_hw_access and the lockdep check that comes with it. Signed-off-by:
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Eric Huang authored
To fullfill the reset event description. Suggested-by:
Eric Huang <jinhuieric.huang@amd.com> Reviewed-by:
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Eric Huang authored
amdgpu_job_ring may return NULL, which causes kernel NULL pointer error, using another way to print ring name instead of ring->name. Suggested-by:
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Aric Cyr authored
This version brings the following changes: - Add sequential ONO sequencing for DCN35 - Add new GPINT command definitions - reduce ODM slice count to initial new dc state only when needed - Enable copying of bounding box data from VBIOS DMUB - Guard reading 3DLUT registers for dcn32/dcn35 Reviewed-by:
Aric Cyr <aric.cyr@amd.com> Tested-by:
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Sung Joon Kim authored
[why] There are other factors that determine the number of DSC slices. The slices should not be determined in DML but retrieve the value calculated from driver. [how] Update the logic to determine DSC slice. Make DSCDelay per display pipe. Reviewed-by:
Jun Lei <jun.lei@amd.com> Acked-by:
Sung Joon Kim <sungjoon.kim@amd.com> Tested-by:
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Alex Hung authored
Two additional virtual links are created and thus increasing size for dc->links by two. Reviewed-by:
Alvin Lee <alvin.lee2@amd.com> Acked-by:
Alex Hung <alex.hung@amd.com> Tested-by:
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Nicholas Kazlauskas authored
[Why] 3DLUT is not part of the DPP on DCN32/DCN35 ASIC and these registers now exist in MCM state. [How] Add guards when reading DPP state based on whether the register has a valid offset. Reviewed-by:
Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Tested-by:
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Dillon Varone authored
- Ensure SubVP stream settings match ODM policy - Fix MALL size calculations when DCC is enabled - Fail if any stream fails DRR policy check Reviewed-by:
Chaitanya Dhere <chaitanya.dhere@amd.com> Acked-by:
Dillon Varone <dillon.varone@amd.com> Tested-by:
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Alvin Lee authored
[Description] In newer DCN's the programming of SYMCLK_FE_SRC_SEL depends on the value of DIG_FE_SOURCE_SELECT. If DIG_FE_SOURCE_SELECT is not already programmed at the time of PHY / DIG enable then the FW sequence will program an incorrect SYMCLK source. Ensure that we program DIG_FE_SOURCE_SELECT for all DIO scenarios (DVI in this particular case) before going through the PHY / DIG enable sequence. Reviewed-by:
Wenjing Liu <wenjing.liu@amd.com> Acked-by:
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Jesse Zhang authored
Since the range of the varibable i is 0 - 3. So execution cannot reach this statement: default. Signed-off-by:
Jesse Zhang <Jesse.Zhang@amd.com> Reviewed-by:
Tim Huang <Tim.Huang@amd.com> Signed-off-by:
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