- 06 Sep, 2017 6 commits
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Corey Minyard authored
The MIPS frame save code was just saving a few registers, enough to do a backtrace if every function set up a frame. However, this is not working if you are using DWARF unwinding, because most of the registers are wrong. This was causing kdump backtraces to be short or bogus. So save all the registers. Signed-off-by:
Corey Minyard <cminyard@mvista.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/16989/Signed-off-by:
Ralf Baechle <ralf@linux-mips.org>
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Corey Minyard authored
This will allow kdump dumps to work correclty with MIPS and future DWARF unwinding of the stack to give accurate tracebacks. Signed-off-by:
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Corey Minyard authored
Modify the SAVE_SOME macro to look more like a standard function, doing the arithmetic for the frame on the SP register instead of copying it from K1, and by saving the stored EPC from the RA. This lets the get_frame_info() function process this function like any other. It also remove an instruction or two from the kernel entry, making it more efficient. unwind_stack_by_address() has special handling for the top of the interrupt stack, but without this change unwinding will still fail if you get an interrupt while handling an interrupt and try to do a traceback from the second interrupt. This change modifies the get_saved_sp macro to optionally store the fetched value right into sp and store the old SP value into K0. Then it's just a matter of subtracting the frame from SP and storing the old SP from K0. This required changing the DADDI workaround a bit, since K0 holds the SP, we had to use K1 for AT. But it eliminated some of the special handling for the DADDI workaround. Saving the RA register was moved up to before fetching the CP0_EPC register, so the CP0_EPC register could be stored into RA and the saved. This lets the traceback code know where RA is actually stored. Signed-off-by:
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Corey Minyard authored
I saw two problems when doing backtraces: The compiler was putting a "fast return" at the top of some functions, before it set up the frame. The backtrace code would stop when it saw a jump instruction, so it would never get to the stack frame setup and would thus misinterpret it. To fix this, don't look for jump instructions until the frame setup has been seen. The assembly code here is: ffffffff80b885a0 <serial8250_handle_irq>: ffffffff80b885a0: c8a00003 bbit0 a1,0x0,ffffffff80b885b0 <serial8250_handle_irq+0x10> ffffffff80b885a4: 0000102d move v0,zero ffffffff80b885a8: 03e00008 jr ra ffffffff80b885ac: 00000000 nop ffffffff80b885b0: 67bdffd0 daddiu sp,sp,-48 ffffffff80b885b4: ffb00008 sd s0,8(sp) The second problem was the compiler was putting the last instruction of the frame save in the delay slot of the jump instruction. If it saved the RA in there, the backtrace could would miss it and misinterpret the frame. To fix this, make sure to process the instruction after the first jump seen. The assembly code for this is: ffffffff80806fd0 <plat_irq_dispatch>: ffffffff80806fd0: 67bdffd0 daddiu sp,sp,-48 ffffffff80806fd4: ffb30020 sd s3,32(sp) ffffffff80806fd8: 24130018 li s3,24 ffffffff80806fdc: ffb20018 sd s2,24(sp) ffffffff80806fe0: 3c12811c lui s2,0x811c ffffffff80806fe4: ffb10010 sd s1,16(sp) ffffffff80806fe8: 3c11811c lui s1,0x811c ffffffff80806fec: ffb00008 sd s0,8(sp) ffffffff80806ff0: 3c10811c lui s0,0x811c ffffffff80806ff4: 08201c03 j ffffffff8080700c <plat_irq_dispa tch+0x3c> ffffffff80806ff8: ffbf0028 sd ra,40(sp) Signed-off-by:
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Mathieu Malaterre authored
The jz4740-rtc driver supports both jz4740 & jz4780, setup the compatible string to jz4780. Signed-off-by:
Mathieu Malaterre <malat@debian.org> Cc: Rob Herring <robh+dt@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Linus Walleij <linus.walleij@linaro.org> Cc: Paul Cercueil <paul@crapouillou.net> Cc: Krzysztof Kozlowski <krzk@kernel.org> Cc: devicetree@vger.kernel.org Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/17237/Signed-off-by:
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Mathieu Malaterre authored
Update the Ci20's defconfig to enable the JZ4780's RTC driver. Signed-off-by:
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- 04 Sep, 2017 34 commits
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Carlos Munoz authored
Signed-off-by:
Carlos Munoz <carlos.munoz@caviumnetworks.com> Signed-off-by:
Steven J. Hill <steven.hill@cavium.com> Acked-by:
David Daney <david.daney@cavium.com> Acked-by:
Guenter Roeck <linux@roeck-us.net> Cc: linux-mips@linux-mips.org Cc: linux-watchdog@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/17214/Signed-off-by:
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David Daney authored
Signed-off-by:
Carlos Munoz <cmunoz@caviumnetworks.com> Signed-off-by:
Chandrakala Chavva <cchavva@caviumnetworks.com> Acked-by:
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Steven J. Hill authored
* Update copyright and company name. * Remove unused headers. * Fix variable spelling and data type. * Use octal values for module parameters. Signed-off-by:
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Steven J. Hill authored
Add accessor function octeon_irq_get_block_domain() for cores with a CIU3. Signed-off-by:
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Steven J. Hill authored
Updates CSR read/write functions to be aware of nodes present in systems with CIU3 support. Signed-off-by:
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Steven J. Hill authored
Signed-off-by:
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Steven J. Hill authored
Signed-off-by:
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Steven J. Hill authored
Used by the Octeon watchdog driver to get the address of the firmware boot vector. Signed-off-by:
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Martin Blumenstingl authored
The RCU register are now access through separates drivers. remove the last pieces of the old implementation. The GPHY reset bits are now set by the GPHY driver which registers a reboot notifier. The reboot is triggered by a syscon-reboot driver and the MIPS specific parts are done by the generic MIPS implementation in arch/mips/kernel/reset.c. Signed-off-by:
Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by:
Hauke Mehrtens <hauke@hauke-m.de> Cc: john@phrozen.org Cc: robh@kernel.org Cc: andy.shevchenko@gmail.com Cc: p.zabel@pengutronix.de Cc: kishon@ti.com Cc: mark.rutland@arm.com Cc: linux-mips@linux-mips.org Cc: linux-mtd@lists.infradead.org Cc: linux-watchdog@vger.kernel.org Cc: devicetree@vger.kernel.org Cc: linux-spi@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/17131/Signed-off-by:
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Hauke Mehrtens authored
This is now done in a PHY driver. Signed-off-by:
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Hauke Mehrtens authored
This driver starts the DWC2 core(s) built into the XWAY SoCs and provides the PHY interfaces for each core. The phy instances can be passed to the dwc2 driver, which already supports the generic phy interface. Signed-off-by:
Kishon Vijay Abraham I <kishon@ti.com> Acked-by:
Rob Herring <robh@kernel.org> Cc: martin.blumenstingl@googlemail.com Cc: john@phrozen.org Cc: andy.shevchenko@gmail.com Cc: p.zabel@pengutronix.de Cc: mark.rutland@arm.com Cc: linux-mips@linux-mips.org Cc: linux-mtd@lists.infradead.org Cc: linux-watchdog@vger.kernel.org Cc: devicetree@vger.kernel.org Cc: linux-spi@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/17127/Signed-off-by:
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Hauke Mehrtens authored
The GPHY loader was replaced by a new more flexible driver. Remove the old driver. Signed-off-by:
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Martin Blumenstingl authored
Compared to the old xrx200_phy_fw driver the new version has multiple enhancements. The name of the firmware files does not have to be added to all .dts files anymore - one now configures the GPHY mode (FE or GE) instead. Each GPHY can now also boot separate firmware (thus mixing of GE and FE GPHYs is now possible). The new implementation is based on the RCU syscon-mfd and uses the reeset_controller framework instead of raw RCU register reads/writes. Signed-off-by:
Andy Shevchenko <andy.shevchenko@gmail.com> Acked-by:
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Hauke Mehrtens authored
This code is now replaced by a reset controller in drivers/reset/reset- lantiq-rcu.c. The old code was never used anyway. Signed-off-by:
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Martin Blumenstingl authored
The reset controllers (on xRX200 and newer SoCs have two of them) are provided by the RCU module. This was initially implemented as a simple reset controller. However, the RCU module provides more functionality (ethernet GPHYs, USB PHY, etc.), which makes it a MFD device. The old reset controller driver implementation from arch/mips/lantiq/xway/reset.c did not honor this fact. For some devices the request and the status bits are different. Signed-off-by:
Philipp Zabel <p.zabel@pengutronix.de> Acked-by:
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Ralf Baechle authored
This will only be used until the last usage of ltq_boot_select() has been removed. Signed-off-by: -
Hauke Mehrtens authored
Do not export the ltq_reset_cause() and ltq_boot_select() function any more. ltq_reset_cause() was accessed by the watchdog driver before to see why the last reset happened, this is now done through direct access of the register over regmap. The bits in this register are anyway different between the xrx200 and the falcon SoC. ltq_boot_select() is not used any more and was used by the flash drivers to check if the system was booted from this flash type, now the drivers should depend on the device tree only. Signed-off-by:
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Hauke Mehrtens authored
Instead of hacking the configuration of the FPI bus into the arch code add an own bus driver for this internal bus. The FPI bus is the main bus of the SoC. This bus driver makes sure the bus is configured correctly before the child drivers are getting initialized. This driver will probably also be used on different SoCs later. Signed-off-by:
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Hauke Mehrtens authored
This adds the initial documentation for the RCU module (a MFD device which provides USB PHYs, reset controllers and more). The RCU register range is used for multiple purposes. Mostly one device uses one or multiple register exclusively, but for some registers some bits are for one driver and some other bits are for a different driver. With this patch all accesses to the RCU registers will go through syscon. Signed-off-by:
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Martin Blumenstingl authored
Signed-off-by:
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Hauke Mehrtens authored
The binding was not documented before, add the documentation now. Signed-off-by:
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Hauke Mehrtens authored
This patch avoids accessing the function ltq_reset_cause() and directly accesses the register given over the syscon interface. The syscon interface will be implemented for the xway SoCs for the falcon SoCs the ltq_reset_cause() function never worked, because a wrong offset was used. Signed-off-by:
Guenter Roeck <linux@reck-us.net> Cc: martin.blumenstingl@googlemail.com Cc: john@phrozen.org Cc: robh@kernel.org Cc: andy.shevchenko@gmail.com Cc: p.zabel@pengutronix.de Cc: kishon@ti.com Cc: mark.rutland@arm.com Cc: linux-mips@linux-mips.org Cc: linux-mtd@lists.infradead.org Cc: linux-watchdog@vger.kernel.org Cc: devicetree@vger.kernel.org Cc: linux-spi@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/17123/Signed-off-by:
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Hauke Mehrtens authored
Do not check which flash type the SoC was booted from before using this driver. Assume that the device tree is correct and use this driver when it was added to device tree. This also removes a build dependency to the SoC code. Signed-off-by:
Brian Norris <computersforpeace@gmail.com> Cc: martin.blumenstingl@googlemail.com Cc: john@phrozen.org Cc: robh@kernel.org Cc: andy.shevchenko@gmail.com Cc: p.zabel@pengutronix.de Cc: kishon@ti.com Cc: mark.rutland@arm.com Cc: linux-mips@linux-mips.org Cc: linux-mtd@lists.infradead.org Cc: linux-watchdog@vger.kernel.org Cc: devicetree@vger.kernel.org Cc: linux-spi@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/17117/Signed-off-by:
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Martin Blumenstingl authored
This allows populating syscon devices which are using "simple-mfd" instead of "simple-bus". Signed-off-by:
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Paul Burton authored
gic_set_affinity() manually copies the provided cpumask to the struct irq_common_data affinity field, returning IRQ_SET_MASK_OK_NOCOPY in order to prevent the core code from doing that. We can instead simply let the core code do it for us, by returning IRQ_SET_MASK_OK instead of IRQ_SET_MASK_OK_NOCOPY & doing the copy ourselves. [ralf@linux-mips.org: Resolve merge conflict.] Signed-off-by:
Paul Burton <paul.burton@imgtec.com> Acked-by:
Marc Zyngier <marc.zyngier@arm.com> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/17056/Signed-off-by:
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Paul Burton authored
Currently in gic_set_affinity() we calculate a temporary cpumask holding the intersection of the provided cpumask & the CPUs that are online, then we call cpumask_first twice on it to find the first such CPU. Since we don't need the temporary cpumask for anything else & we only care about the first CPU that's both online & in the provided cpumask, we can instead use cpumask_first_and to find that CPU & drop the temporary mask. Signed-off-by:
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Paul Burton authored
When parsing mti,reserved-cpu-vectors we generate a mask of all bits that have been declared reserved, the loop through starting from bit 2 to find one that isn't reserved (ie. is zero). This patch accomplishes the same task more simply by: - Inititialising the reserved mask to 0x3 (ie. the 2 software interrupts). This means we don't need to skip them later as the loop previously has. - Replacing the loop checking for zero bits with find_first_zero_bit, which fits our needs now that the 2 software interrupts are marked reserved. This requires that the type of reserved is changed to unsigned long so that it's suitable for use with bitmap functions. - Replacing the magic number 8 with the hamming weight of the ST0_IM field - ie. the number of bits that a MIPS CPU has for interrupt inputs. This is still a compile-time constant 8, but makes it clearer why it's 8. Signed-off-by: -
Paul Burton authored
This patch avoids the need to read the GIC_SH_MASK* registers when decoding shared interrupts by setting & clearing the interrupt's bit in the appropriate CPU's pcpu_masks entry when masking or unmasking the interrupt. This effectively means that whilst an interrupt is masked we clear its bit in all pcpu_masks, which causes gic_handle_shared_int() to ignore it on all CPUs without needing to check GIC_SH_MASK*. In essence, we add a little overhead to masking or unmasking interrupts but in return reduce the overhead of the far more common task of decoding interrupts. Signed-off-by:
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Paul Burton authored
Define the pcpu_masks variable using the kernel's standard per-cpu variable support, rather than an open-coded array of structs containing bitmaps. Signed-off-by:
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Paul Burton authored
gic_basic_init() is now a fairly short function that is only called in one place. Inline it into gic_of_init() to help readability. [ralf@linux-mips.org: Resolved conflict.] Signed-off-by:
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Paul Burton authored
The __gic_init() function is only called from gic_of_init() now that the non-DT path has been removed. In order to simplify the code & aid readability, fold __gic_init() into gic_of_init(). This provides us with the ability to return an error code, which __gic_init() was previously unable to do. As such the irq_domain_add_*() error paths are modified to print & return an error rather than panic(). [ralf@linux-mips.org: Resoled reject.] Signed-off-by:
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Paul Burton authored
The linux/irqchip/mips-gic.h header is no longer used. Remove it. Signed-off-by:
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Paul Burton authored
linux/irqchip/mips-gic.h is included in a few files that don't actually use it at all. Remove these unnecessary inclusions in preparation for removing the header. Signed-off-by:
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Paul Burton authored
Our VDSO code makes use of macros from linux/irqchip/mips-gic.h to provide offsets to register values, but these are trivial offsets to the two 32 bit halves of a 64 bit value. Replace use of the macros with zero (ie. omit adding an offset) and the size of the low 32 bit of the value. This removes our need for linux/irqchip/mips-gic.h & prepares us for it to be removed. Signed-off-by:
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