- 10 Dec, 2020 40 commits
-
-
YouChing Lin authored
The Macronix MX35LF2GE4AD / MX35LF4GE4AD are 3V, 2G / 4Gbit serial SLC NAND flash device (with on-die ECC). Validated by read, erase, read back, write, read back and nandtest on Xilinx Zynq PicoZed FPGA board which included Macronix SPI Host (drivers/spi/spi-mxic.c). Signed-off-by:
YouChing Lin <ycllin@mxic.com.tw> Signed-off-by:
Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/1604561020-13499-1-git-send-email-ycllin@mxic.com.tw
-
Baskov Evgeiny authored
If an error happens in mtd_device_parse_register or mtd_device_register, memory allocated for struct platram_info is leaked. Make platram_probe() call platram_remove() on all error paths after struct platram_info allocation to correctly free resources. Found by Linux Driver Verification project (linuxtesting.org). Signed-off-by:
Baskov Evgeiny <baskov@ispras.ru> Signed-off-by:
-
Thomas Gleixner authored
struct mtd_info has a flag oops_panic_write which is set when the write operation is issued via the panic_write() callback. That allows controller drivers to distinguish the panic write from a regular write. Replace the open coded 'in_interrupt() | oops_in_progress' checks with a check for that flag. in_interrupt() is an unrealiable indicator anyway as it covers all sorts of atomic contexts not only hard and soft interrupt service routines. Signed-off-by:
Thomas Gleixner <tglx@linutronix.de> Signed-off-by:
Sebastian Andrzej Siewior <bigeasy@linutronix.de> Cc: Vignesh Raghavendra <vigneshr@ti.com> Cc: Tudor Ambarus <tudor.ambarus@microchip.com> Cc: Richard Weinberger <richard@nod.at> Cc: Kyungmin Park <kyungmin.park@samsung.com> Cc: Boris Brezillon <boris.brezillon@collabora.com> Cc: linux-mtd@lists.infradead.org Cc: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by:
-
Miquel Raynal authored
The raw NAND core now declares the on host ECC engine being the default if none is provided in the DT. Drop this line doing exactly the same from the Marvell driver. Signed-off-by:
-
Miquel Raynal authored
When the nand_chip structure is already available, there is no need to dereference it through the info pointer. Use the chip pointer directly in this case. Signed-off-by:
-
Miquel Raynal authored
While working a bit on this driver I dropped the platform includes and commented a few lines just to verify the correctness of my changes. It appeared the following: drivers/mtd/nand/raw/au1550nd.c: In function ‘au1550nd_waitrdy’: drivers/mtd/nand/raw/au1550nd.c:130:3: error: implicit declaration of function ‘usleep_range’ [-Werror=implicit-function-declaration] usleep_range(10, 100); ^~~~~~~~~~~~ drivers/mtd/nand/raw/au1550nd.c: In function ‘au1550nd_exec_instr’: drivers/mtd/nand/raw/au1550nd.c:188:3: error: implicit declaration of function ‘ndelay’ [-Werror=implicit-function-declaration] ndelay(instr->delay_ns); ^~~~~~ I think the delay.h header should be included in this file and not come from one of its platform includes, so let's add it here. Signed-off-by:
-
Miquel Raynal authored
The NAND ECC core is included in the generic NAND core when it is compiled in. Different software ECC engines drivers will select the NAND ECC core and thus also have a dependency on the NAND core. Using a "depends on" between the two leads to possible cases (not real cases, but created by robots) where one is still unselected because of the "select does not verifies depends on" game: WARNING: unmet direct dependencies detected for MTD_NAND_ECC Depends on [n]: MTD [=m] && MTD_NAND_CORE [=n] Selected by [m]: - MTD_NAND_ECC_SW_HAMMING [=y] && MTD [=m] - MTD_NAND_ECC_SW_BCH [=y] && MTD [=m] Fix this by using a select instead. Reported-by:
Randy Dunlap <rdunlap@infradead.org> Signed-off-by:
-
Miquel Raynal authored
Moving files around produced the following warnings: Error: Cannot open file drivers/mtd/nand/raw/nand_ecc.c Error: Cannot open file drivers/mtd/nand/raw/nand_ecc.c Fix one by just dropping the reference because it is not relevant, the other by using a better noun instead of a file name. Signed-off-by: -
Fabio Estevam authored
i.MX is a devicetree-only platform now and the existing platform data support in this driver was only useful for old non-devicetree platforms. Get rid of the platform data support since it is no longer used. Signed-off-by:
Fabio Estevam <festevam@gmail.com> Reviewed-by:
Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by:
-
Yu Kuai authored
of_find_device_by_node() already takes a reference to the device, and ingenic_ecc_release() will drop the reference. So, the get_device() in ingenic_ecc_get() is redundand. Fixes: 15de8c6e("mtd: rawnand: ingenic: Separate top-level and SoC specific code") Signed-off-by:
Yu Kuai <yukuai3@huawei.com> Acked-by:
Paul Cercueil <paul@crapouillou.net> Signed-off-by:
-
Miquel Raynal authored
This code has been written in 2008 and is fine, but in order to keep robots happy, I think it's time to change a little bit this code just to clarify the different possible values of eccsize_mult. Indeed, this variable may only take the value 1 or 2 because step_size, in the case of the software Hamming ECC engine may only be 256 or 512. Depending on the value of eccsize_mult, an extra rp17 variable is set, or not and triggers the following warning: smatch warnings: ecc_sw_hamming_calculate() error: uninitialized symbol 'rp17'. As highlighted by Dan Carpenter, if the only possible values for eccsize_mult are 1 and 2, then the code is fine, but "it's hard to tell just from looking". So instead of shifting step_size, let's use a ternary condition to assign to eccsize_mult the only two possible values and clarify the driver's logic. Now that the situation is clarified for humans, ensure rp17 is initialized to 0 to keep compilers and robots silent as well. Reported-by:kernel test robot <lkp@intel.com> Reported-by:
Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by:
-
Manuel Dipolt authored
This patch enables NAND MDMA (MBUS DMA) mode for the Allwinner SoCs A23/A33/H3. The DMA transfer method gets sets now to MBUS DMA as default for the sun8i-a23-nand-controller (till now DMA transfer was executed via the shared DMA engine). The main advantage is more bandwidth for the users of the shared DMA engine and also that the MBUS DMA setup requires less configuration effort. For example you don't need to define a dedicated DMA channel in the device-tree any more. Reviewed-by:
Boris Brezillon <boris.brezillon@collabora.com> Signed-off-by:
Manuel Dipolt <manuel.dipolt@robart.cc> Signed-off-by:
-
Sergei Antonov authored
Arguments 'infolen' and 'datalen' to meson_nfc_dma_buffer_release() were mixed up. Fixes: 8fae856c ("mtd: rawnand: meson: add support for Amlogic NAND flash controller") Cc: stable@vger.kernel.org Signed-off-by:
Sergei Antonov <saproj@gmail.com> Acked-by:
Liang Yang <liang.yang@amlogic.com> Signed-off-by:
-
Mauro Carvalho Chehab authored
Some identifiers have different names between their prototypes and the kernel-doc markup. Signed-off-by:
Mauro Carvalho Chehab <mchehab+huawei@kernel.org> Signed-off-by:
-
Kathiravan T authored
Add the compatible string for IPQ6018 QPIC NAND controller version 1.5.0. It's properties are same as IPQ8074, so reuse the same. Signed-off-by:
Kathiravan T <kathirav@codeaurora.org> Signed-off-by:
-
Kathiravan T authored
Add the binding for the QPIC NAND used on IPQ6018 SoC. Signed-off-by:
Rob Herring <robh@kernel.org> Signed-off-by:
-
Praveenkumar I authored
After each codeword NAND_FLASH_STATUS is read for possible operational failures. But there is no DMA sync for CPU operation before reading it and this leads to incorrect or older copy of DMA buffer in reg_read_buf. This patch adds the DMA sync on reg_read_buf for CPU before reading it. Fixes: 5bc36b2b ("mtd: rawnand: qcom: check for operation errors in case of raw read") Cc: stable@vger.kernel.org Signed-off-by:
Praveenkumar I <ipkumar@codeaurora.org> Signed-off-by:
-
Marco Felsch authored
The extra gpmi_nand.o object is not needed anymore since commit 3045f8e3 ("mtd: rawnand: gpmi: move all driver code into single file"). Signed-off-by:
Marco Felsch <m.felsch@pengutronix.de> Signed-off-by:
-
Miquel Raynal authored
This comment is no longer true so drop it. Signed-off-by:
-
Miquel Raynal authored
So far OOB have never been used in SPI-NAND, add the missing memcpy to make it work properly. Fixes: 7529df46 ("mtd: nand: Add core infrastructure to support SPI NANDs") Cc: stable@vger.kernel.org Signed-off-by:
-
Miquel Raynal authored
Even if this is not supposed to happen, there is no reason to fail the probe if it was explicitly requested to use no ECC engine at all (for instance, during development). This condition is met by just commenting out the error on the OOB free bytes count after the assignation of an ECC engine if none was provided (any other situation would error out much earlier anyway). Signed-off-by:
-
Miquel Raynal authored
Now that all the logic is available in the NAND core, let's use it from the SPI-NAND core. Right now there is no functional change as the default ECC engine for SPI-NANDs is set to 'on-die', but user can now use software correction if they want to by just setting the right properties in the DT. Also note that the OOB layout handling is removed from the SPI-NAND core as each ECC engine is supposed to handle it by it's own; users should not be aware of that. Signed-off-by:
-
Miquel Raynal authored
This property does not describe very well its purpose: it describes the ECC engine type. Deprecate it in favor of nand-ecc-engine which points to either the NAND part itself in case of on-die ECC, or to the parent node in case of an integrated ECC engine in the NAND controller (previously referred as "hardware") or to another node in case of an external controller. Other "modes" (none/software) are achieved with the new nand-use-soft-ecc-engine and nand-no-ecc-engine properties. Signed-off-by:
-
Miquel Raynal authored
Add the logic in the NAND core to find the right ECC engine depending on the NAND chip requirements and the user desires. Right now, the choice may be made between (more will come): * software Hamming * software BCH * on-die (SPI-NAND devices only) Once the ECC engine has been found, the ECC engine must be configured. Signed-off-by:
-
Miquel Raynal authored
The SPI-NAND layer default is on-die ECC because until now it was the only one supported. New SPI-NAND chip flavors might use something else as ECC engine provider but this will always be the default if the user does not choose explicitly something else. Signed-off-by:
-
Miquel Raynal authored
Before making use of the ECC engines, we must retrieve them. Add the necessary boilerplate. Signed-off-by:
-
Miquel Raynal authored
Make use of the existing functions taken from the SPI-NAND core to instantiate an on-die ECC engine specific to the SPI-NAND core. The next step will be to tweak the core to use this object instead of calling the helpers directly. Signed-off-by:
-
Miquel Raynal authored
Prepare the creation of a SPI-NAND on-die ECC engine by gathering the ECC-related code earlier enough in the core to avoid the need for forward declarations. The next step is to actually create that engine by implementing the generic ECC interface. Signed-off-by:
-
Miquel Raynal authored
One comment in the SPI-NAND core is not very clear, fix it to ease the understanding of what the block does. Signed-off-by:
-
Miquel Raynal authored
Before making use of the ECC engines, we must retrieve them. Add the boilerplate for the ones already available: software engines (Hamming and BCH). Signed-off-by:
-
Miquel Raynal authored
Let's continue introducing the generic ECC engine abstraction in the NAND subsystem by instantiating a second ECC engine: software Hamming. Signed-off-by:
-
Miquel Raynal authored
There is no reason to always embed the software Hamming ECC engine implementation. By default it is (with raw NAND), but we can let the user decide. Signed-off-by:
-
Miquel Raynal authored
Most of the includes are simply useless, drop them. Signed-off-by:
-
Miquel Raynal authored
This code is meant to be reused by the SPI-NAND core. Now that the driver has been cleaned and reorganized, use a generic ECC engine object to store the driver's data instead of accessing members of the nand_chip structure. This means adding proper init/cleanup helpers. Signed-off-by:
-
Miquel Raynal authored
Prefix by ecc_sw_hamming_ the functions which should be internal only but are exported for "raw" operations. Prefix by nand_ecc_sw_hamming_ the other functions which will be used in the context of the declaration of an Hamming proper ECC engine object. Signed-off-by:
-
Miquel Raynal authored
Various style fixes. There is not functional change. Signed-off-by:
-
Miquel Raynal authored
Some functions should never have been exported (the ones prefixed by __*), in this case simply drop the documentation, we never want anybody to use this function from the outside. For the other functions, enhance the style. Signed-off-by:
-
Miquel Raynal authored
The include file pretends being the header for "ECC algorithm", while it is just the header for the Hamming implementation. Make this clear by rewording the sentence. Do the same with the module description. Signed-off-by:
-
Miquel Raynal authored
Hamming ECC code might be later re-used by the SPI NAND layer. Signed-off-by:
-
Miquel Raynal authored
nand_ecc_ctrl embeds a private pointer which only has a meaning in the sunxi driver. This structure will soon be deprecated, but as this field is actually not needed, let's just drop it. Cc: Maxime Ripard <mripard@kernel.org> Cc: Chen-Yu Tsai <wens@csie.org> Signed-off-by:
Maxime Ripard <mripard@kernel.org> Link: https://lore.kernel.org/linux-mtd/20200929230124.31491-11-miquel.raynal@bootlin.com
-
