- 23 Feb, 2024 9 commits
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Serge Semin authored
Without having the putc() prototype forwardly declared the next build-warning is printed: arch/mips/boot/compressed/uart-prom.c:6:6: warning: no previous prototype for ‘putc’ [-Wmissing-prototypes] ... Fix that by adding the "decompress.h" header file with the putc() function declaration to the source files which have the method redefined. Signed-off-by:
Serge Semin <fancer.lancer@gmail.com> Signed-off-by:
Thomas Bogendoerfer <tsbogend@alpha.franken.de>
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Jiaxun Yang authored
c994a3ec ("MIPS: set mips32r5 for virt extensions") setted some instructions in virt extensions to ISA level mips32r5. However TLB related vz instructions was leftover, also this shouldn't be done to a R5 or R6 kernel buid. Reorg macros to set ISA level as needed when _ASM_SET_VIRT is called. Signed-off-by:
Jiaxun Yang <jiaxun.yang@flygoat.com> Signed-off-by:
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Jiaxun Yang authored
Implement various microMIPS MT ASE helpers accroading to: MIPS
® Architecture for Programmers Volume IV-f: The MIPS® MT Module for the microMIPS32™ Architecture Fixes build error: {standard input}:2616: Error: branch to a symbol in another ISA mode This make MT ASE available on microMIPS as well. Boot tested on M5150 with microMIPS enabled on M5150. Signed-off-by: -
Jiaxun Yang authored
MIPS MT ASE is only available on ISA between Release 1 and Release 5. Add ISA level dependency to Kconfig to fix build. Reported-by:
Guenter Roeck <linux@roeck-us.net> Signed-off-by:
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Jiaxun Yang authored
Currently march flag is hardcoded to loongson3a for GCC and mips64r2 for clang. We can actually test it to simplify the code. Signed-off-by:
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Jiaxun Yang authored
Nowadays GCC will always pass -march flag to gas, so there is no need to pass another mips32 flag to assembler. Signed-off-by:
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Jiaxun Yang authored
LLVM does not implement some of -march options. However those options are not mandatory for kernel to build for those CPUs. Fallback -march CFLAG to ISA level if unsupported by toolchain so we can get those kernel to build with LLVM. Link: https://github.com/ClangBuiltLinux/linux/issues/1544Reported-by:
Nathan Chancellor <nathan@kernel.org> Signed-off-by:
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Jiaxun Yang authored
Nowadays our minimal supported GCC/Clang all support -march=octeon. Remove cc-option checks to simplify code. Signed-off-by:
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Jiaxun Yang authored
msym32 is not supported by LLVM toolchain. Workaround by probe toolchain support of msym32 for KBUILD_SYM32 feature. Link: https://github.com/ClangBuiltLinux/linux/issues/1544Signed-off-by:
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- 20 Feb, 2024 31 commits
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Ilpo Järvinen authored
Instead of literal, PCI error value should be set with PCI_SET_ERROR_RESPONSE(). Use it in tx4927_pci_config_read(). Signed-off-by:
Ilpo Järvinen <ilpo.jarvinen@linux.intel.com> Reviewed-by:
Sergio Paracuellos <sergio.paracuellos@gmal.com> Signed-off-by:
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Ilpo Järvinen authored
pci_ops .read/.write must return PCIBIOS_* codes but tx4927_pci_config_read/write() return -1 when mkaddr() cannot find devfn from the root bus. Return PCIBIOS_DEVICE_NOT_FOUND instead and pass that onward in the call chain instead of overwriting the return value. Also converts 0 -> PCIBIOS_SUCCESSFUL which has only cosmetic impact. Signed-off-by:
Sergio Paracuellos <sergio.paracuellos@gmail.com> Reviewed-by:
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Ilpo Järvinen authored
pcibios_plat_dev_init() is called from pcibios_enable_device() that should return normal errnos, not PCIBIOS return codes. In this case the impact is only cosmetic because PCIBIOS_SUCCESSFUL equals 0 that is success code with errnos as well. Nonetheless, remove the inconsistency by replacing the PCIBIOS_SUCCESSFUL with 0. Signed-off-by:
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Ilpo Järvinen authored
Ever since introduction in the commit e47d4889 ("MIPS: Lantiq: Add PCI controller support.") ltqpci_plat_dev_init has been unused. In 57c8cb8f ("MIPS: pci: convert lantiq driver to OF") also ltq_pci_plat_arch_init was introduced. With those commit being more than 10 years ago, it seem neither is going to get used anytime soon. Thus, remove both unused function pointer variables. Signed-off-by:
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Ricardo B. Marliere authored
Now that the driver core can properly handle constant struct bus_type, move the mips_cdmm_bustype variable to be a constant structure as well, placing it into read-only memory which can not be modified at runtime. Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Suggested-by:
Greg Kroah-Hartman <gregkh@linuxfoundation.org> Signed-off-by:
Ricardo B. Marliere <ricardo@marliere.net> Reviewed-by:
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Ricardo B. Marliere authored
Since commit d492cc25 ("driver core: device.h: make struct bus_type a const *"), the driver core can properly handle constant struct bus_type, move the tc_bus_type variable to be a constant structure as well, placing it into read-only memory which can not be modified at runtime. Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Suggested-by:
Maciej W. Rozycki <macro@orcam.me.uk> Reviewed-by:
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Ricardo B. Marliere authored
Now that the driver core can properly handle constant struct bus_type, move the txx9_sramc_subsys variable to be a constant structure as well, placing it into read-only memory which can not be modified at runtime. Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Suggested-by:
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Ricardo B. Marliere authored
Now that the driver core can properly handle constant struct bus_type, move the gio_bus_type variable to be a constant structure as well, placing it into read-only memory which can not be modified at runtime. Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Suggested-by:
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Masahiro Yamada authored
Move the following entries out of the "CPU type" choice: - LOONGSON3_ENHANCEMENT - CPU_LOONGSON3_WORKAROUNDS - CPU_LOONGSON3_CPUCFG_EMULATION These entries cannot be selected from the choice because they depend on CPU_LOONGSON64, which is also located in the same choice. In fact, Kconfig does not consider them as choice values because they become children of CPU_LOOONGSON64 due to the automatic submenu creation in menu_finalize(). However, it is hard to understand this behavior unless you are familiar with the Kconfig internals. "choice" should contain only selectable entries. Signed-off-by:
Masahiro Yamada <masahiroy@kernel.org> Reviewed-by:
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Erick Archer authored
As noted in the "Deprecated Interfaces, Language Features, Attributes, and Conventions" documentation [1], size calculations (especially multiplication) should not be performed in memory allocator (or similar) function arguments due to the risk of them overflowing. This could lead to values wrapping around and a smaller allocation being made than the caller was expecting. Using those allocations could lead to linear overflows of heap memory and other misbehaviors. So, use the purpose specific kcalloc() function instead of the argument size * count in the kzalloc() function. Link: https://www.kernel.org/doc/html/next/process/deprecated.html#open-coded-arithmetic-in-allocator-arguments [1] Link: https://github.com/KSPP/linux/issues/162Signed-off-by:
Erick Archer <erick.archer@gmx.com> Reviewed-by:
Gustavo A. R. Silva <gustavoars@kernel.org> Signed-off-by:
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Serge Semin authored
Add myself as a maintainer of the MIPS Baikal-T1 platform-specific drivers. The arch-code hasn't been submitted yet, but will be soon enough. Until then it's better to have the already available drivers marked as maintained. Signed-off-by:
Serge Semin <Sergey.Semin@baikalelectronics.ru> Signed-off-by:
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Gregory CLEMENT authored
Add Vlad, Théo and myself as co-maintainers for the Mobileye MIPS SoCs. Signed-off-by:
Vladimir Kondratiev <vladimir.kondratiev@mobileye.com> Signed-off-by:
Théo Lebrun <theo.lebrun@bootlin.com> Signed-off-by:
Gregory CLEMENT <gregory.clement@bootlin.com> Signed-off-by:
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Gregory CLEMENT authored
Introduce support for the MIPS based Mobileye EyeQ5 SoCs. Reviewed-by:
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Gregory CLEMENT authored
Some architectures might seek to utilize a significant portion of the generic kernel code while maintaining independence from the generic kernel due to specific peculiarities. This patch allows for the reuse of core code, preventing unnecessary duplication. Suggested-by:
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Gregory CLEMENT authored
Add a device tree for the Mobileye EPM5 evaluation board. Reviewed-by:
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Gregory CLEMENT authored
Add a device tree include file for the Mobileye EyeQ5 SoC. Based on the work of Slava Samsonov <stanislav.samsonov@intel.com> Signed-off-by:
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Gregory CLEMENT authored
Add the yaml bindings for Mobileye SoCs. Currently only EyeQ5 is supported Reviewed-by:
Rob Herring <robh@kernel.org> Signed-off-by:
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Gregory CLEMENT authored
The MIPS Warrior I-class I6500 was announced by Imagination Technologies in 2016 and is used in the Mobileye SoC EyeQ5. Acked-by:
Arnd Bergmann <arnd@arndb.de> Reviewed-by:
Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by:
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by:
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Gregory CLEMENT authored
The entries were nearly sorted but there were still some entries at the wrong places. Let's fix it. Reviewed-by:
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Gregory CLEMENT authored
Mobileye Vision Technologies Ltd. is a company developing autonomous driving technologies and advanced driver-assistance systems (ADAS) including cameras, computer chips and software. Reviewed-by:
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Gregory CLEMENT authored
Some access are 32 bits only while they seems better to be done in 64bis for 64 bit kernel. This was extract from an initial patch from Jiaxun Co-developed-by:
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Gregory CLEMENT authored
With the expanded support for placing the kernel in XPHYS rather than just KSEG0, scenarios where ebase doesn't belong to KSEG0 are more likely to occur. In such cases, we currently experience a substantial and perplexing stack dump without any accompanying explanation. To rectify this, we aim to replace the uninformative stack dump with a warning that offers a clear explanation of the issue. Reviewed-by:
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Jiaxun Yang authored
Now the exception vector for CPS systems are allocated on-fly with memblock as well. It will try to allocate from KSEG1 first, and then try to allocate in low 4G if possible. The main reset vector is now generated by uasm, to avoid tons of patches to the code. Other vectors are copied to the location later. move 64bits fix in an other patch fix cache issue with mips_cps_core_entry rewrite the patch to reduce the diff stat move extern in header use cache address for copying vector gc: use the new macro CKSEG[0A1]DDR_OR_64BIT() Signed-off-by: -
Jiaxun Yang authored
ebase might reside in XKPHYS if memblock is unable to allocate memory within the KSEG0 physical range. To map EBASE into uncached space, we convert it back to its physical address and utilize the new CKSEG1ADDR_OR_64BIT helper for mapping. Co-developed-by:
Vladimir Kondratiev <vladimir.kondratiev@intel.com> Signed-off-by:
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Gregory CLEMENT authored
Define CKSEGX_SIZE to represent the size of each KSEG segment. Introduce CKSEG0ADDR_OR_64BIT and CKSEG1ADDR_OR_64BIT to get an XPHYS address in 64bits and CKSEG[01]ADDR() in 32 bits mode. Co-developed-by:
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Jiaxun Yang authored
Use GPR number macros in uasm code generation parts to reduce code duplication. There are functional change due to difference in register symbolic names between OABI and NABI, while existing code is only using definitions from OABI. Code pieces are carefully inspected to ensure register usages are safe on NABI as well. We changed register allocation of r_pcohctl from T7 to T8 as T7 is not available on NABI and we just want a caller saved scratch register here. Signed-off-by:
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Jiaxun Yang authored
Use GPR number macros in uasm code generation parts to reduce code duplication. No functional change. Signed-off-by:
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Jiaxun Yang authored
Use GPR number macros in uasm code generation parts to reduce code duplication. No functional change. Signed-off-by:
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Jiaxun Yang authored
Use GPR number macros in uasm code generation parts to reduce code duplication. No functional change. Signed-off-by:
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Jiaxun Yang authored
Use GPR number macros in uasm code generation parts to reduce code duplication. No functional change. Signed-off-by:
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Jiaxun Yang authored
Define a set of register numbers with their symbolic names to help with uasm code. All names are prefixed by GPR_ to prevent naming clash. Signed-off-by:
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