- 17 May, 2018 40 commits
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Alex Deucher authored
Adds additional gfx configuration data. v2: fix typo Acked-by:
Christian König <christian.koenig@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Jerry (Fangzhi) Zuo authored
Retrieve fuses to determine the availability of pipes, and eliminate pipes that cannot be used. Acked-by:
Jerry (Fangzhi) Zuo <Jerry.Zuo@amd.com> Reviewed-by:
Hersen Wu <hersenxs.wu@amd.com> Reviewed-by:
Tony Cheng <Tony.Cheng@amd.com> Reviewed-by:
Feifei Xu <Feifei.Xu@amd.com>
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Jerry (Fangzhi) Zuo authored
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Feifei Xu authored
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Jerry (Fangzhi) Zuo authored
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Harry Wentland <harry.wentland@amd.com> Reviewed-by:
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Roman Li authored
Updating dce12 register headers by adding dc registers required for potential DP LTTPR support. v2: fix mode change Acked-by:
Roman Li <Roman.Li@amd.com> Acked-by:
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Feifei Xu authored
v2: fix whitespace Signed-off-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
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Feifei Xu authored
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Feifei Xu authored
Some register offset in nbio v7.4 are different with v7.0. v2: Use nbio7.0 for now. TODO: add a new nbio 7.4 module (Alex) Signed-off-by:
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Feifei Xu authored
Same as vega10 now. v2: squash in typo fix Reviewed-by:
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Feifei Xu authored
Vega20 need a seperate vega20_reg_init.c due to ip base offset difference. Reviewed-by:
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Feifei Xu authored
Same as vega10 for now. Reviewed-by:
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Feifei Xu authored
Set external_rev_id and disable cg,pg for now. Reviewed-by:
Huang Rui <ray.huang@amd.com> Signed-off-by:
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Feifei Xu authored
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Feifei Xu authored
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Feifei Xu authored
v2: clean up (Alex) v3: additional cleanups (Alex) v4: drop leftover TODO (Alex) Signed-off-by:
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Feifei Xu authored
v2: squash in updates (Alex) v3: squash in more updates (Alex) Acked-by:
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Feifei Xu authored
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Feifei Xu authored
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Feifei Xu authored
v2: squash in updates (Alex) v3: squash in more updates (Alex) Reviewed-by:
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Feifei Xu authored
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Feifei Xu authored
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Feifei Xu authored
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Feifei Xu authored
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Feifei Xu authored
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Feifei Xu authored
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Feifei Xu authored
The same as vega10. Reviewed-by:
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Feifei Xu authored
The same as vega10 for now. Reviewed-by:
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Feifei Xu authored
Initial powerplay support the same as vega10 for now. Reviewed-by:
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Feifei Xu authored
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Feifei Xu authored
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Feifei Xu authored
vega20_gpu_info firmware stores gpu configuration for vega20. v2: drop gpu info firmware for vega20 Squash of: drm/amdgpu: Add gpu_info firmware for vega20. drm/amdgpu: drop gpu_info firmware for vega20 Reviewed-by:
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Feifei Xu authored
Add vega20 to amd_asic_type enum and amdgpu_asic_name[]. Reviewed-by:
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James Zhu authored
Vega20 uses vce 4.1 engine, all the registers have the same absolute offset with vce 4.0. By adjusting vega20 VCE_BASE, vce 4.1 can reuse vce 4.0 header files. Signed-off-by:
James Zhu <James.Zhu@amd.com> Reviewed-by:
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Feifei Xu authored
This headerfile contains vega20's ip base addresses. v2: squash in MP1_BASE fix Acked-by:
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Feifei Xu authored
In gmc_v9_0_vram_gtt_location(),the vram_base_offset is hardcoded to 0 in dGPU. Fix it by reading mmMC_VM_FB_OFFSET or return zfb_phys_addr if ZFB is enabled. Signed-off-by:
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Feifei Xu authored
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Evan Quan authored
configuration change settings Signed-off-by:
Evan Quan <evan.quan@amd.com> Reviewed-by:
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Evan Quan authored
This is needed for vega12 and vega20 which do not support legacy powerstate. With this new framework, the DAL clocks limits can also be honored on these asics. Signed-off-by:
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Feifei Xu authored
Update golden_settings_gc_9_0[]. Signed-off-by:
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