- 19 May, 2011 40 commits
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Ralf Baechle authored
It never really belonged into syscall.c and it's about to become well more complex. Signed-off-by:Ralf Baechle <ralf@linux-mips.org>
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Ralf Baechle authored
As noticed by Kevin Cernekee <cernekee@gmail.com> in http://www.linux-mips.org/cgi-bin/extract-mesg.cgi?a=linux-mips&m=2011-05&i=BANLkTikq04wuK%3Dbz%2BLieavmm3oDtoYWKxg%40mail.gmail.com Patchwork: https://patchwork.linux-mips.org/patch/2387/Signed-off-by:
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David Daney authored
We only use the three low-order mailbox bits. Leave the upper bits alone for possible use by drivers and other software. Signed-off-by:
David Daney <ddaney@caviumnetworks.com> To: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2090/Signed-off-by:
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Chandrakala Chavva authored
Octeon uses different interrupt irq for timer and performance counters. Set CvmCtl[IPPCI] to correct irq value very early. Signed-off-by:
Chandrakala Chavva <cchavva@caviumnetworks.com> Signed-off-by:
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Wanlong Gao authored
Since d45dcef7 ["Bluetooth: Fix BT_L2CAP and BT_SCO in Kconfig"] BT_L2CAP=m and BT_SCO=m are no longer valid so change the settings from m to y. [ralf@linux-mips.org: Merging only the MIPS parts of this patch.] Signed-off-by:
Wanlong Gao <wanlong.gao@gmail.com> To: akpm@linux-foundation.org To: manuel.lauss@googlemail.com Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Cc: linux-mips@linux-mips.org Cc: linuxppc-dev@lists.ozlabs.org Patchwork: https://patchwork.linux-mips.org/patch/2277/Signed-off-by:
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Wanlong Gao authored
Since 5ada28bf ["led-class: always implement blinking"] LEDS_CLASS=m is no longer valid so change the setting from m to y. Signed-off-by:
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Robert Millan authored
Signed-off-by:
Robert Millan <rmh@gnu.org> Acked-by:
Kevin Cernekee <cernekee@gmail.com> Cc: David Daney <ddaney@caviumnetworks.com> Cc: wu zhangjin <wuzhangjin@gmail.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/2302/Signed-off-by:
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Kevin Cernekee authored
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Robert Millan authored
Replace these sequences: if (cpu == 0) __elf_platform = "foo"; with a trivial inline function. Signed-off-by:
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Maarten ter Huurne authored
Assume that the boot loader knows the physical memory of the system and deduce that information from the contents of the SDRAM control register. It is still possible to override with with the "mem=" parameter, but we have a sensible default now. Signed-off-by:
Maarten ter Huurne <maarten@treewalker.org> Acked-by:
Lars-Peter Clausen <lars@metafoo.de> Cc: linux-kernel@vger.kernel.org Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2319/Signed-off-by:
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Hauke Mehrtens authored
Some devices like the Netgear WGT634u are using minuses between the blocks of the MAC address and other devices are using colons to separate them. Signed-off-by:
Hauke Mehrtens <hauke@hauke-m.de> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2366/Signed-off-by:
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Hauke Mehrtens authored
Some members of the struct ssb_sprom where not filled with data available in the NVRAM. Some attribute names in the NVRAM changed from SPROM version 3 to version 4. This patch was done by analyzing the the pci sprom parser in the ssb code and some open source parts of the braodcom wireless driver used on embedded devices. Signed-off-by:
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Hauke Mehrtens authored
We are generating the prefix based on the PCI bus address the device is on. This is done like Broadcom does it in their code expect that the the bus number is increased by one. In the SB bus implementation used by Broadcom the SB bus emulates a PCI bus so the kernel sees one PCI bus more then in our implementation. We do not handle prefixes like sb/1/ yet as they are only used on the new bus which is not implemented yet. Signed-off-by:
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Hauke Mehrtens authored
When an other SSB based device without an own SPROM is attached, using the PCI bus to the main SSB based device, the data normally found in the SPROM will be stored in the NVRAM on modern devices. The keys, to load the data from the NVRAM, are all using some sort of prefix like pci/1/1/, pci/1/3/ or sb/1/ before the actual key. This patch extends bcm47xx_fill_sprom() to make it possible to read out these values when some prefix was used. The keys for the SPROM data used on the main chip does not have a prefix. Signed-off-by:
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Hauke Mehrtens authored
Some embedded devices like the Netgear WNDR3300 have two SSB based cards without an own sprom on the pci bus. We have to provide two different fallback sproms for these and this was not possible with the old solution. In the bcm47xx architecture the sprom data is stored in the nvram in the main flash storage. The architecture code will be able to fill the sprom with the stored data based on the bus where the device was found. The bcm63xx code should do the same thing as before, just using the new API. Acked-by:
Michael Buesch <mb@bu3sch.de> Cc: netdev@vger.kernel.org Cc: linux-wireless@vger.kernel.org Cc: Florian Fainelli <florian@openwrt.org> Signed-off-by:
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Manuel Lauss authored
remove au_readl/au_writel, remove the predefined GPIO1/2 KSEG1 register addresses and fix the fallout in all boards and drivers. This also fixes a bug in the mtx-1_wdt driver which was introduced by commit 6ea8115b ("Convert mtx1 wdt to be a platform device and use generic GPIO API") before this patch mtx-1_wdt only modified GPIO215, the patch then used the gpio resource information as bit index into the GPIO2 register but the conversion to the GPIO API didn't realize that. With this patch the drivers original behaviour is restored and GPIO15 is left alone. Signed-off-by:
Manuel Lauss <manuel.lauss@googlemail.com> Cc: Florian Fainelli <florian@openwrt.org> To: Linux-MIPS <linux-mips@linux-mips.org> Cc: linux-watchdog@vger.kernel.org Cc: Wim Van Sebroeck <wim@iguana.be> Patchwork: https://patchwork.linux-mips.org/patch/2381/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org
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Manuel Lauss authored
According to the databooks, the Au1000 DMA engine must be programmed with the physical FIFO addresses. This patch does that; furthermore this opened the possibility to get rid of a lot of now unnecessary address defines. Signed-off-by:
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Manuel Lauss authored
Rewrite ethernet setup to use runtime cpu detection, and also clean up the ethernet base address mess as far as possible. Signed-off-by:
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Manuel Lauss authored
Detect CPU type at runtime and setup uarts accordingly; also clean up the uart base address mess in the process as far as possible. Signed-off-by:
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Manuel Lauss authored
Convert the PM sysdev to syscore_ops and clean up the ddma addresses a bit. Signed-off-by:
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Manuel Lauss authored
Convert the PM sysdev to use syscore_ops instead. Signed-off-by:
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Manuel Lauss authored
replace au_readl/au_writel with __raw_readl/__raw_writel, and clean up IC-related stuff from the headers. Signed-off-by:
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Manuel Lauss authored
This fixes a build failure with gpio_keys and CONFIG_GPIOLIB=n (mtx1): CC drivers/input/keyboard/gpio_keys.o gpio_keys.c: In function 'gpio_keys_report_event': gpio_keys.c:325:2: error: implicit declaration of function 'gpio_get_value_cansleep' gpio_keys.c: In function 'gpio_keys_setup_key': gpio_keys.c:390:3: error: implicit declaration of function 'gpio_set_debounce' Also add stubs for the other new functions. Signed-off-by:
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Manuel Lauss authored
Setting Config[OD] gets rid of a _LOT_ of spurious CPLD interrupts, but also decreases overall performance a bit. Signed-off-by:
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Ralf Baechle authored
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Ralf Baechle authored
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Ralf Baechle authored
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John Crispin authored
This patch adds the driver for the watchdog found inside the Lantiq SoC family. Signed-off-by:
John Crispin <blogic@openwrt.org> Signed-off-by:
Ralph Hempel <ralph.hempel@lantiq.com> Cc: Wim Van Sebroeck <wim@iguana.be> Cc: linux-mips@linux-mips.org Cc: linux-watchdog@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/2327/Signed-off-by:
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John Crispin authored
Register the etop platform device inside the machtype specific init code. Signed-off-by:
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John Crispin authored
This patch adds the driver for the ETOP Packet Processing Engine (PPE32) found inside the XWAY family of Lantiq MIPS SoCs. This driver makes 100MBit ethernet work. Support for all 8 dma channels, gbit and the embedded switch found on the ar9/vr9 still needs to be implemented. Signed-off-by:
David S. Miller <davem@davemloft.net> Signed-off-by:
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John Crispin authored
This patch adds support for the DMA engine found inside the XWAY family of SoCs. The engine has 5 ports and 20 channels. Signed-off-by:
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John Crispin authored
Signed-off-by:
Felix Fietkau <nbd@openwrt.org> Cc: alan@lxorguk.ukuu.org.uk Cc: linux-mips@linux-mips.org Cc: linux-serial@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/2269/Acked-by:
Alan Cox <alan@linux.intel.com> Signed-off-by:
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John Crispin authored
The XWAY family allows to extend the number of gpios by using shift registers or latches. This patch adds the 2 drivers needed for this. The extended gpios are output only. [ralf@linux-mips.org: Fixed ltq_stp_probe section() attributes.] Signed-off-by:
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John Crispin authored
This patch adds mach specific code for the Lantiq EASY50712/50601 evaluation boards Signed-off-by:
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John Crispin authored
This patch adds support for Gabor's mips_machine patch. Signed-off-by:
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John Crispin authored
This patch adds the wrappers for registering our platform devices. Signed-off-by:
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John Crispin authored
This patch adds the driver/map for NOR devices attached to the SoC via the External Bus Unit (EBU). Signed-off-by:
Artem Bityutskiy <dedekind1@gmail.com> Patchwork: https://patchwork.linux-mips.org/patch/2285/Signed-off-by:
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John Crispin authored
The Lantiq family of SoCs have a EBU (External Bus Unit). This patch adds the driver that allows us to use the EBU as a PCI controller. In order for PCI to work the EBU is set to endianess swap all the data. In addition we need to make use of SWAP_IO_SPACE for device->host DMA to work. The clock of the PCI works in several modes (internal/external). If this is not configured correctly the SoC will hang. Signed-off-by:
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John Crispin authored
Add support for the Lantiq XWAY family of Mips24KEc SoCs. * Danube (PSB50702) * Twinpass (PSB4000) * AR9 (PSB50802) * Amazon SE (PSB5061) The Amazon SE is a lightweight SoC and has no PCI as well as a different clock. We split the code out into seperate files to handle this. The GPIO pins on the SoCs are multi function and there are several bits we can use to configure the pins. To be as compatible as possible to GPIOLIB we add a function int lq_gpio_request(unsigned int pin, unsigned int alt0, unsigned int alt1, unsigned int dir, const char *name); which lets you configure the 2 "alternate function" bits. This way drivers like PCI can make use of GPIOLIB without a cubersome wrapper. The PLL code inside arch/mips/lantiq/xway/clk-xway.c is voodoo to me. It was taken from a 2.4.20 source tree and was never really changed by me since then. Signed-off-by: -
John Crispin authored
Add initial support for Mips based SoCs made by Lantiq. This series will add support for the XWAY family. The series allows booting a minimal system using a initramfs or NOR. Missing drivers and support for Amazon and GPON family will be provided in a later series. [Ralf: Remove some cargo cult programming and fixed formatting.] Signed-off-by:
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