- 29 Feb, 2016 40 commits
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Russell King authored
When we get a response CRC error on a command, it means that the response we received back from the card was not correct. It does not mean that the card did not receive the command correctly. If the command is one which initiates a data transfer, the card can enter the data transfer state, and start sending data. Moreover, if the request contained a data phase, we do not clean this up, and this results in the driver triggering DMA API debug warnings, and also creates a race condition in the driver, between running the finish_tasklet and the data transfer interrupts, which can trigger a "Got data interrupt" state dump. Fix this by handing a response CRC error slightly differently: record the failure of the data initiating command, but allow the remainder of the request to be processed normally. This is safe as core MMC checks the status of all commands and data transfer phases of the request. If the card does not initiate a data transfer, then we should time out according to the data transfer parameters. Signed-off-by:
Russell King <rmk+kernel@arm.linux.org.uk> [ Fix missing parenthesis around bitwise-AND expression, and tweak subject ] Signed-off-by:
Adrian Hunter <adrian.hunter@intel.com> Cc: stable@vger.kernel.org # v4.5+ Tested-by:
Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by:
Ulf Hansson <ulf.hansson@linaro.org>
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Russell King authored
Avoid multiple tests while handling a command error; simplify the code. Signed-off-by:
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Russell King authored
When a command is started, logically it has no error. Initialise the command's error member to zero whenever we start a command. Signed-off-by:
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Ulf Hansson authored
up the maintainer role for SDHCI. I am very pleased that Adrian Hunter volunteered and accepted the challenge! The SDHCI code is currently in quite poor quality, but we have agreed on a way forward to try to reach a point where the SDHCI core becomes more of a set of library functions. Each SDHCI driver variant can then decide which functions to use and allows it to implement variant specific code, without needing to also change SDHCI core code. In the end we aim to get better optimized and maintainable code. Signed-off-by:
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Al Cooper authored
sdhci_add_host() allows the Host Controller Capability registers to be supplied by the calling driver by using SDHCI_QUIRK_MISSING_CAPS, but the check for the Capabilities bit SDHCI_CAN_64BIT doesn't use the applied value and instead reads the Host register directly. This change uses the supplied "caps" register instead of reading the host register. This change will allow a calling driver to simply clear the SDHCI_CAN_64BIT bit in "caps" to handle some cases of SDHCI_QUIRK2_BROKEN_64_BIT_DMA. Signed-off-by:
Al Cooper <alcooperx@gmail.com> Acked-by:
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Andrei Pistirica authored
This driver supports the SDHCI host controller found on a PIC32. Signed-off-by:
Andrei Pistirica <andrei.pistirica@microchip.com> Signed-off-by:
Joshua Henderson <joshua.henderson@microchip.com> Cc: Ralf Baechle <ralf@linux-mips.org> Signed-off-by:
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Andrei Pistirica authored
Document the devicetree bindings for the SDHCI peripheral found on Microchip PIC32 class devices. Signed-off-by:
Rob Herring <robh@kernel.org> Signed-off-by:
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Shawn Lin authored
This patch make num_slots to 1 if pdata->num_slot is not defined. Meanwhile, we need to make sure num_slots should not larger that the supported slots Signed-off-by:
Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by:
Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by:
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Shawn Lin authored
dw_mci_probe clear interrupts and disable all interrupts firstly. While it clear interrupt again before enable some interrupts. We can't see any reason to clear it twice here, so remove the second one. Signed-off-by:
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Shawn Lin authored
This patch add correct err handle if dw_mci_ctrl_reset failed while probing. Signed-off-by:
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Shawn Lin authored
dw_mmc already use mmc_of_parse to get "broken-cd" property, but it considered "broken-cd" to be a quirk in its driver. We don't need this quirk here, and just take what we need from mmc->caps. Signed-off-by:
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Shawn Lin authored
This patch removes struct block_settings since it's never used anywhere. Signed-off-by:
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Shawn Lin authored
This patch implement hw_reset function for DesignWare MMC controller. By adding this feature, mmc blk can do some basic recovery. Set the following resets: software reset – BMOD[0] for IDMAC only DMA reset - CTRL[2] FIFO reset - CTRL[1] bits Program the CARD_RESET register with a value of 0 for the bit corresponding to the card number; This programming asserts the RST_n signal and resets the card. After a minimum of 1 ?s, de-asserts the RST_n signal and takes the card out of reset. The application can program a new CMD only after a minimum of 200 us This implementation can be easily tested by cutting off->On vmmc while doing data accessing in background to simulate that case. Signed-off-by:
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Jaehoon Chung authored
This patch removes the prepare_command hook from entire dw_mmc driver. Now, almost all SoCs are using by default, except Exynos. It seems that dwmmc controller is using unnecessary hook. To know whether needs to set this bit or not, add the DW_MMC_CARD_NO_USE_HOLD bit. If some SoCs need to disable this in future, just set the DW_MMC_CARD_NO_USE_HOLD bit. set_bit(DW_MMC_CARD_NO_USE_HOLD, &slot->flags), Signed-off-by:
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Russell King authored
Print the error code when the tuning command fails. This allows the reason for the failure to be reported, which aids debugging. Signed-off-by:
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Russell King authored
Re-tuning is part of standard requirements for the higher speed SD card protocols, and is not an error when this occurs. When we retry a command due to a retune, we should not print a message to the kernel log. Signed-off-by:
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Russell King authored
Improve mmc_of_parse_voltage()'s return values so that drivers can tell whether a voltage-range specification was present, and whether it has been successfully parsed, or there was an error while parsing. We return a negative errno when parsing fails, zero if no voltage-range specification is present, or one if a voltage-range specification is successfully parsed. No users need modifying as no users check the return value. Signed-off-by:
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Russell King authored
Each time a driver such as sdhci-esdhc-imx is probed, we get a info printk complaining that the DT voltage-ranges property has not been specified. However, the DT binding specifically says that the voltage-ranges property is optional. That means we should not be complaining that DT hasn't specified this property: by indicating that it's optional, it is valid not to have the property in DT. Silence the warning if the property is missing. Signed-off-by:
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Wolfram Sang authored
Rcar2 & 3 docs state that for going to and coming from the 0xff setting, the clock must first be disabled before the DIV bits are changed. Instead of tracking this, let's just do this unconditionally. Signed-off-by:
Wolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by:
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Wolfram Sang authored
Some of the indentation made the code awful to read. Fix that. Also, introduce defines instead of magic hex values. Note that this includes one change: We mask out know 0xff instead of 0x1ff. But 0x100 has always been the clock enable bit. It doesn't make any sense to set it depending on the clock calculation. Update copyright notices, too. I'll be working on those files some more in the future. Signed-off-by:
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Wolfram Sang authored
Signed-off-by:
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Wolfram Sang authored
These don't make sense anymore. Since commit 5d60e500 ("mmc: tmio: add new TMIO_MMC_HAVE_HIGH_REG flags"), we don't deal with a resource here. Signed-off-by:
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Wolfram Sang authored
The docs for RCar Gen2 & 3 I have access to, mention delays of 5ms after stop and 1ms after start. Make it possible to apply these values. Signed-off-by:
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Wolfram Sang authored
We will get a full dump anyhow. Signed-off-by:
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Shinobu Uehara authored
All the docs I have access to say that this register needs the bus busy check. Signed-off-by:
Shinobu Uehara <shinobu.uehara.xc@renesas.com> Signed-off-by:
Ai Kyuse <ai.kyuse.uw@renesas.com> Signed-off-by:
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Wolfram Sang authored
When compiling the driver with CONFIG_MMC_DEBUG set, I got build warnings. They have been 'fixed' meanwhile. However, because these debug messages look random anyhow (some duplicate information printed etc), let's just drop them and rather re-add something consistent if that should ever be needed. Signed-off-by:
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Jaehoon Chung authored
After removed the MMC_DATA_STREAM, only two flags are remained. (MMC_DATA_READ and MMC_DATA_WRITE) The flags of READ and WRITE can't be used together. That's why it doesn't need to use "OR' operation. Signed-off-by:
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Jaehoon Chung authored
It's not set to MMC_DATA_STREAM anywhere. It seems that it had been used with CMD11/CMD20. But according to Spec, CMD11/CMD20 are obsolete command. Signed-off-by:
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Jaehoon Chung authored
Remove the MMC_DATA_STREAM flag because it isn't used anymore. Signed-off-by:
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Jaehoon Chung authored
Remove the MMC_DATA_STREAM flag because it isn't used anymore. Signed-off-by:
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Jaehoon Chung authored
Remove the MMC_DATA_STREAM flag because it isn't used anymore. Signed-off-by:
Robert Jarzmik <robert.jarzmik@free.fr> Signed-off-by:
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Jaehoon Chung authored
Remove the MMC_DATA_STREAM flag because it isn't used anymore. Signed-off-by:
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Jaehoon Chung authored
Remove the MMC_DATA_STREAM flag because it isn't used anymore. Signed-off-by:
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Jaehoon Chung authored
Remove the MMC_DATA_STREAM flag because it isn't used anymore. Signed-off-by:
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Jaehoon Chung authored
Remove the MMC_DATA_STREAM flag because it isn't used anymore. Signed-off-by:
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Jaehoon Chung authored
Remove the MMC_DATA_STREAM flag because it isn't used anymore. Signed-off-by:
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Jaehoon Chung authored
Remove the MMC_DATA_STREAM flag because it isn't used anymore. Signed-off-by:
Ludovic Desroches <ludovic.desroches@atmel.com> Signed-off-by:
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Chen-Yu Tsai authored
Now that clock delay settings for 8 bit DDR are correct, and vqmmc support is available, we can enable MMC_CAP_1_8V_DDR support. This enables MMC HS-DDR at up to 52 MHz, even if signal voltage switching is not available. Signed-off-by:
Chen-Yu Tsai <wens@csie.org> Reviewed-by:
Hans de Goede <hdegoede@redhat.com> Signed-off-by:
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Chen-Yu Tsai authored
Allwinner's MMC controller needs to run at double the card clock rate for 8 bit DDR transfer modes. Interestingly, this is not needed for 4 bit DDR transfers. Different clock delays are needed for 8 bit eMMC DDR, due to the increased module clock rate. For the A80 though, the same values for 4 bit and 8 bit are shared. The new values for the other SoCs were from A83T user manual's "new timing mode" default values, which describes them in clock phase, rather than delay periods. These values were used without any modification. They may not be correct, but they work. Signed-off-by:
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Chen-Yu Tsai authored
DDR transfer modes include UHS-1 DDR50 and MMC HS-DDR (or MMC_DDR52). Consider MMC_DDR52 when setting clock delays. Since MMC high speed mode goes up to 52 MHz instead of 50 MHz for SD, and this number is visible in the capability macro, increase the clock rate upper limit to 52 MHz. Signed-off-by:
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