- 29 Aug, 2022 1 commit
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Guchun Chen authored
Below driver load error will be printed, not friendly to end user. amdgpu: ATOM BIOS: 113-D603GLXE-077 [drm] FRU: Failed to get size field [drm:amdgpu_fru_get_product_info [amdgpu]] *ERROR* Failed to read FRU Manufacturer, ret:-5 Signed-off-by:
Guchun Chen <guchun.chen@amd.com> Reviewed-by:
Kent Russell <kent.russell@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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- 25 Aug, 2022 32 commits
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Bernard Zhao authored
This patch fix cocci warning: drivers/gpu/drm/amd/display/dc/dcn314/dcn314_resource.c:1816:6-8: WARNING: possible condition with no effect (if == else). Signed-off-by:
Bernard Zhao <bernard@vivo.com> Signed-off-by:
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Bernard Zhao authored
This patch fix cocci warning: drivers/gpu/drm/amd/display/dc/core/dc.c:3335:2-4: WARNING: possible condition with no effect (if == else). Signed-off-by:
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Bernard Zhao authored
This patch fix potential memory leak (clk_src) when function run into last return NULL. Signed-off-by:
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Bernard Zhao authored
This patch fix potential memory leak (clk_src) when function run into last return NULL. s/free/kfree/ - Alex Signed-off-by:
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Qu Huang authored
The mmVM_L2_CNTL3 register is not assigned an initial value Signed-off-by:
Qu Huang <jinsdb@126.com> Signed-off-by:
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Rafael J. Wysocki authored
According to the ACPI specification [1], the ACPI_FADT_LOW_POWER_S0 flag merely means that it is better to use low-power S0 idle on the given platform than S3 (provided that the latter is supported) and it doesn't preclude using either of them (which of them will be used depends on the choices made by user space). However, on some systems that flag is used to indicate whether or not to enable special firmware mechanics allowing the system to save more energy when suspended to idle. If that flag is unset, doing so is generally risky. Accordingly, add a comment to explain the ACPI_FADT_LOW_POWER_S0 check in amdgpu_acpi_is_s0ix_active(), the purpose of which is otherwise somewhat unclear. Link: https://uefi.org/specs/ACPI/6.4/05_ACPI_Software_Programming_Model/ACPI_Software_Programming_Model.html#fixed-acpi-description-table-fadt # [1] Reviewed-by:
Mario Limonciello <mario.limonciello@amd.com> Signed-off-by:
Rafael J. Wysocki <rafael.j.wysocki@intel.com> Signed-off-by:
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Yu Zhe authored
time_after() deals with timer wrapping correctly. Signed-off-by:
Yu Zhe <yuzhe@nfschina.com> Signed-off-by:
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Guchun Chen authored
'free PSP TMR buffer' happens in suspend, but sometimes in mGPU config, it mixes with PSP resume log printing from another GPU, which is confusing. So use dev_info instead of DRM_INFO for printing. [drm] PSP is resuming... [drm] reserve 0xa00000 from 0x877e000000 for PSP TMR amdgpu 0000:e3:00.0: amdgpu: GECC is enabled amdgpu 0000:e3:00.0: amdgpu: SECUREDISPLAY: securedisplay ta ucode is not available amdgpu 0000:e3:00.0: amdgpu: SMU is resuming... amdgpu 0000:e3:00.0: amdgpu: smu driver if version = 0x00000040, smu fw if version = 0x00000041, smu fw program = 0, version = 0x003a5400 (58.84.0) amdgpu 0000:e3:00.0: amdgpu: SMU driver if version not matched amdgpu 0000:e3:00.0: amdgpu: dpm has been enabled amdgpu 0000:e3:00.0: amdgpu: SMU is resumed successfully! [drm] DMUB hardware initialized: version=0x02020014 [drm] free PSP TMR buffer [drm] kiq ring mec 2 pipe 1 q 0 Signed-off-by:
Evan Quan <evan.quan@amd.com> Signed-off-by:
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Guchun Chen authored
adev_to_drm is used everywhere in amdgpu code, so modify it to keep consistency. Signed-off-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
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Likun Gao authored
Enable GFX11 MGCG perfmon setting. V2: set rlc to saft mode before setting. Signed-off-by:
Likun Gao <Likun.Gao@amd.com> Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
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Chengming Gui authored
Avoid soft reset, even ip hang check (ring/ib test) when gpu recovery disabled. v2: add missing "}" Signed-off-by:
Chengming Gui <Jack.Gui@amd.com> Reviewed-by:
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Prike Liang authored
Correct the isa version for handling KFD test. Fixes: 7c4f4f19 ("drm/amdkfd: Add GC 10.3.6 and 10.3.7 KFD definitions") Signed-off-by:
Prike Liang <Prike.Liang@amd.com> Reviewed-by:
Aaron Liu <aaron.liu@amd.com> Signed-off-by:
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Mukul Joshi authored
When translate_further is enabled, page table depth needs to be updated. This was missing on Arcturus MMHUB init. This was causing address translations to fail for SDMA user-mode queues. Fixes: 352e683b ("drm/amdgpu: Enable translate_further to extend UTCL2 reach") Reviewed-by:
Felix Kuehling <Felix.Kuehling@amd.com> Acked-by:
Mukul Joshi <mukul.joshi@amd.com> Signed-off-by:
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Felix Kuehling authored
Only allocate doorbells when the first queue is created on a GPU or the doorbells need to be mapped into CPU or GPU virtual address space. This avoids allocating doorbells unnecessarily and can allow more processes to use KFD on multi-GPU systems. Signed-off-by:
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Evan Quan authored
To fit the latest 78.53 PMFW. Signed-off-by:
Feifei Xu <Feifei.Xu@amd.com> Signed-off-by:
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Roman Li authored
[Why] We have 2 back-to-back checks for skipping connectors. Logically one of them will do the job. [How] Remove redundant check. Reviewed-by:
Hersen Wu <hersenxs.wu@amd.com>> Acked-by:
Brian Chang <Brian.Chang@amd.com> Signed-off-by:
Roman Li <roman.li@amd.com> Tested-by:
Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by:
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Leo Chen authored
[Why & How] Adding log for clock table from SMU helps with the debugging process. Implemented using DC_LOG_SMU to output log. Reviewed-by:
Charlene Liu <Charlene.Liu@amd.com> Acked-by:
Leo Chen <sancchen@amd.com> Tested-by:
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Alvin Lee authored
[Description] Uncomment scaling cmd assignment since FW headers are now promoted. Reviewed-by:
Martin Leung <Martin.Leung@amd.com> Acked-by:
Alvin Lee <Alvin.Lee2@amd.com> Tested-by:
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Alvin Lee authored
[Why] Sometimes pixel clock needs to remain active after transmitter disable. [How] Use update_phy_state to track PHY state after stream enable/disable and program pixel clock as needed. Reviewed-by:
Taimur Hassan <Syed.Hassan@amd.com> Signed-off-by:
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Alvin Lee authored
[Description] Refcount is incremented on allocation and when adding to the context. Therefore we must release the phantom plane and stream after removing from the context. Reviewed-by:
Aric Cyr <Aric.Cyr@amd.com> Acked-by:
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Aurabindo Pillai authored
[Why&How] When using IGT, kms_bw multi display tests trigger an assert since we ignore virtual signal type. k1/k2 dividers should be correctly programmed if VSYNC needs to be correct. Add the appropriate condition to the if arm to fix this. Reviewed-by:
Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Acked-by:
Aurabindo Pillai <aurabindo.pillai@amd.com> Tested-by:
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Robin Chen authored
[Why] The DAL driver may transmit the wrong cursor position to PSRSU DMUB driver when there are multiple planes. [How] Currently the driver apply the HW cursor on the top plane. So we should only transmit the cursor position on the top plane to PSRSU DMUB driver. Reviewed-by:
Anthony Koo <Anthony.Koo@amd.com> Acked-by:
Robin Chen <po-tchen@amd.com> Tested-by:
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Aurabindo Pillai authored
DC was using compile time initialization of register addresses using SR_* macros and their variants. These have been converted to use runtime initialization. The REG_STRUCT macro is a definition that is added to SR_* macros. During initialization, this must be defined before SR_* macros are invoked, which are in turn invoked through various IP initialization macros. Reviewed-by:
Harry Wentland <Harry.Wentland@amd.com> Acked-by:
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Aurabindo Pillai authored
DC was using compile time initialization of register addresses using SR_* macros and their variants. These have been converted to use runtime initialization. The REG_STRUCT macro is a definition that is added to SR_* macros. During initialization, this must be defined before SR_* macros are invoked, which are in turn invoked through various IP initialization macros. Reviewed-by:
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Ilya Bakoulin authored
[Why] Retrying on receiving a NACK can result in long overall EDID read times in some cases. [How] Retry only on DEFER and return immediately on NACK. Reviewed-by:
Ilya Bakoulin <Ilya.Bakoulin@amd.com> Tested-by:
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Saaem Rizvi authored
[WHY] Reprogramming the stream despite no changes in ODM combine mode. Reprogramming the stream would cause intermittent black screen on display which could only be recovered through enable/disable sequence. [HOW] Fixed bug where we detected a change in ODM combine mode despite ODM combine mode being disabled. Also removed code which required stream to be reprogrammed once a change in ODM combine mode was noticed. Lastly we do not support dynamic ODM switching for HDMI TMDS and FRL on DCN32, therefore we never want to change its ODM policy. Reviewed-by:
Samson Tam <Samson.Tam@amd.com> Acked-by:
Saaem Rizvi <SyedSaaem.Rizvi@amd.com> Tested-by:
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Samson Tam authored
[Why] odm 2:1 policy is splitting the pipes in 4k144. then in subvp code, we merge the pipes. but since the configuration is unsupported, we keep the pipes split [How] for unsupported subvp configuration, redo the dml and pipe split calls Reviewed-by:
Jun Lei <Jun.Lei@amd.com> Acked-by:
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Derek Lai authored
[Why] RV2 do not change pipe split policy in the minimal pipe split transition state. This will unblock mode support on some parts that limit to DPM0 for power reason. [How] Do not change pipe split policy in the minimal pipe split transition state to allow 4k multi display configs to be supported at DPM0. Reviewed-by:
Derek Lai <Derek.Lai@amd.com> Tested-by:
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Aric Cyr authored
This verion brings along following fixes: -Add scaling factor for SubVP -Modify stop_dbg_mode return value -Add gfx_off members and document -Add GFXOFF function for vangogh -Add GFXOFF stats to debug -Fix codestyle problems -Fix overflow on MIN_I64 -Fix Unneeded semicolon -Fix comment typo -Remove useless condition in amdgpu_job_stop_all_jobs_on_sched() -Add decoder_iv_ts helper for ih_v6 -Add chip version to DCN32 -Avoid doing vm_init multiple time -Modify size calculation in MALL -Fix DSC for phantom pipes -Update clock table policy for DCN314 -Modify header inclusion pattern -Fix plug/unplug external monitor will playback MPO video -Add debug parameter to retain default clock table -Increase tlb flush timeout for sriov -Fix compare intergers of different widths -Add reserved dc_log_type -Fix pixel clock programming Acked-by:
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Anthony Koo authored
- For SubVP add scaling factor to allow firmware to calculate accurate line to start programming Reviewed-by:
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Vignesh Chander authored
Skip set_topology_info as xgmi TA will now block it and host needs to program it. Signed-off-by:
Vignesh Chander <Vignesh.Chander@amd.com> Reviewed-By : Shaoyun Liu <Shaoyun.Liu@amd.com> Signed-off-by:
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Tim Huang authored
For some ASICs, like GFX IP v11.0.1, only have one SDMA instance, so not need to configure SDMA1_RLC_CGCG_CTRL for this case. Signed-off-by:
Tim Huang <tim.huang@amd.com> Reviewed-by:
Yifan Zhang <yifan1.zhang@amd.com> Signed-off-by:
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- 22 Aug, 2022 7 commits
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Tales Aparecida authored
Removes DEFINEs that should have been removed after they were introduced to ObjectID.h by the commit abea57d7 ("drm/amdgpu: Add BRACKET_LAYOUT_ENUMs to ObjectID.h") Signed-off-by:
Tales Aparecida <tales.aparecida@gmail.com> Signed-off-by:
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Roman Li authored
[Why] DCN314 supports PCON. [How] Explicitly enable it in dcn314 resources. Signed-off-by:
Hamza Mahfooz <hamza.mahfooz@amd.com> Signed-off-by:
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Tim Huang authored
Enable AMD_CG_SUPPORT_BIF_MGCG and AMD_CG_SUPPORT_BIF_LS support. Signed-off-by:
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Tim Huang authored
Add BIF Clock Gating MGCG and LS support for NBIO IP v7.7.0. Signed-off-by:
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Tim Huang authored
Add the BIF0_PCIE_TX_POWER_CTRL_1 register offset and mask macro definitions for AMD_CG_SUPPORT_BIF_LS. Signed-off-by:
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Zhenneng Li authored
Although radeon card fence and wait for gpu to finish processing current batch rings, there is still a corner case that radeon lockup work queue may not be fully flushed, and meanwhile the radeon_suspend_kms() function has called pci_set_power_state() to put device in D3hot state. Per PCI spec rev 4.0 on 5.3.1.4.1 D3hot State. > Configuration and Message requests are the only TLPs accepted by a Function in > the D3hot state. All other received Requests must be handled as Unsupported Requests, > and all received Completions may optionally be handled as Unexpected Completions. This issue will happen in following logs: Unable to handle kernel paging request at virtual address 00008800e0008010 CPU 0 kworker/0:3(131): Oops 0 pc = [<ffffffff811bea5c>] ra = [<ffffffff81240844>] ps = 0000 Tainted: G W pc is at si_gpu_check_soft_reset+0x3c/0x240 ra is at si_dma_is_lockup+0x34/0xd0 v0 = 0000000000000000 t0 = fff08800e0008010 t1 = 0000000000010000 t2 = 0000000000008010 t3 = fff00007e3c00000 t4 = fff00007e3c00258 t5 = 000000000000ffff t6 = 0000000000000001 t7 = fff00007ef078000 s0 = fff00007e3c016e8 s1 = fff00007e3c00000 s2 = fff00007e3c00018 s3 = fff00007e3c00000 s4 = fff00007fff59d80 s5 = 0000000000000000 s6 = fff00007ef07bd98 a0 = fff00007e3c00000 a1 = fff00007e3c016e8 a2 = 0000000000000008 a3 = 0000000000000001 a4 = 8f5c28f5c28f5c29 a5 = ffffffff810f4338 t8 = 0000000000000275 t9 = ffffffff809b66f8 t10 = ff6769c5d964b800 t11= 000000000000b886 pv = ffffffff811bea20 at = 0000000000000000 gp = ffffffff81d89690 sp = 00000000aa814126 Disabling lock debugging due to kernel taint Trace: [<ffffffff81240844>] si_dma_is_lockup+0x34/0xd0 [<ffffffff81119610>] radeon_fence_check_lockup+0xd0/0x290 [<ffffffff80977010>] process_one_work+0x280/0x550 [<ffffffff80977350>] worker_thread+0x70/0x7c0 [<ffffffff80977410>] worker_thread+0x130/0x7c0 [<ffffffff80982040>] kthread+0x200/0x210 [<ffffffff809772e0>] worker_thread+0x0/0x7c0 [<ffffffff80981f8c>] kthread+0x14c/0x210 [<ffffffff80911658>] ret_from_kernel_thread+0x18/0x20 [<ffffffff80981e40>] kthread+0x0/0x210 Code: ad3e0008 43f0074a ad7e0018 ad9e0020 8c3001e8 40230101 <88210000> 4821ed21 So force lockup work queue flush to fix this problem. Acked-by:
Zhenneng Li <lizhenneng@kylinos.cn> Signed-off-by:
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Magali Lemes authored
dml_wrapper* files were removed in commit 01b537ee ("drm/amd/display: Remove unused code"), as they are not used anywhere. However, the header file wasn't removed, so remove the header as well. Signed-off-by:
Magali Lemes <magalilemes00@gmail.com> Signed-off-by:
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