- 25 Oct, 2021 12 commits
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Cai Huoqing authored
Use the helper macro SET_NOIRQ_SYSTEM_SLEEP_PM_OPS() instead of the verbose operators ".suspend_noirq /.resume_noirq/.freeze_noirq/ .thaw_noirq/.poweroff_noirq/.restore_noirq", because the SET_NOIRQ_SYSTEM_SLEEP_PM_OPS() is a nice helper macro that could be brought in to make code a little clearer, a little more concise. Signed-off-by:
Cai Huoqing <caihuoqing@baidu.com> Link: https://lore.kernel.org/r/20210828090117.1814-1-caihuoqing@baidu.comSigned-off-by:
Vinod Koul <vkoul@kernel.org>
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Dave Jiang authored
Device reset clears the MSIXPERM table and the device registers. Re-program the MSIXPERM table and re-enable the error interrupts post reset. Fixes: 745e92a6 ("dmaengine: idxd: idxd: move remove() bits for idxd 'struct device' to device.c") Reported-by:
Sanjay Kumar <sanjay.k.kumar@intel.com> Signed-off-by:
Dave Jiang <dave.jiang@intel.com> Link: https://lore.kernel.org/r/163054188513.2853562.12077053294595278181.stgit@djiang5-desk3.ch.intel.comSigned-off-by:
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Dave Jiang authored
Add halt interrupt support. Given that the misc interrupt handler already check halt state, the driver just need to run the halt handling code when receiving the halt interrupt. Signed-off-by:
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Angelo Dureghello authored
Fix following panic on system halt: Requesting system halt [ 10.600000] spi spi0.1: spi_device 0.1 cleanup [ 10.630000] fsl_edma_chan_mux() fsl_chan->edma->n_chans 64 dmamux_nr 0 [ 10.630000] *** ZERO DIVIDE *** FORMAT=4 [ 10.630000] Current process id is 38 [ 10.630000] BAD KERNEL TRAP: 00000000 [ 10.630000] PC: [<402f09ba>] fsl_edma_chan_mux+0x7c/0x12e ... Some architecture as mcf5441x (ColdFire) may not have a dmamux, so dmamux_nr is set to 0. This patch considers this case. Signed-off-by:
Angelo Dureghello <angelo.dureghello@timesys.com> Link: https://lore.kernel.org/r/20210901211610.662077-1-angelo.dureghello@timesys.comSigned-off-by:
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Bixuan Cui authored
Using list_move_tail() instead of list_del() + list_add_tail() Reported-by:
Hulk Robot <hulkci@huawei.com> Signed-off-by:
Bixuan Cui <cuibixuan@huawei.com> Acked-by:
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Arnd Bergmann authored
The ptdma driver has added debugfs support, but this fails to build when debugfs is disabled: drivers/dma/ptdma/ptdma-debugfs.c: In function 'ptdma_debugfs_setup': drivers/dma/ptdma/ptdma-debugfs.c:93:54: error: 'struct dma_device' has no member named 'dbg_dev_root' 93 | debugfs_create_file("info", 0400, pt->dma_dev.dbg_dev_root, pt, | ^ drivers/dma/ptdma/ptdma-debugfs.c:96:55: error: 'struct dma_device' has no member named 'dbg_dev_root' 96 | debugfs_create_file("stats", 0400, pt->dma_dev.dbg_dev_root, pt, | ^ drivers/dma/ptdma/ptdma-debugfs.c:102:52: error: 'struct dma_device' has no member named 'dbg_dev_root' 102 | debugfs_create_dir("q", pt->dma_dev.dbg_dev_root); | ^ Remove the #ifdef in the header, as this only saves a few bytes, but would require ugly #ifdefs in each driver using it. Simplify the other user while we're at it. Fixes: e2fb2e2a ("dmaengine: ptdma: Add debugfs entries for PTDMA") Fixes: 26cf132d ("dmaengine: Create debug directories for DMA devices") Signed-off-by:Arnd Bergmann <arnd@arndb.de> Reviewed-by:
Laurent Pinchart <laurent.pinchart@ideasonboard.com> Link: https://lore.kernel.org/r/20210920122017.205975-1-arnd@kernel.orgSigned-off-by:
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Dave Jiang authored
Fault triggers on ioread32() when pci driver unbind is envoked. The placement of idxd sub-driver removal causes the probing of the device mmio region after the mmio mapping being torn down. The driver needs the sub-drivers to be unbound but not release the idxd context until all shutdown activities has been done. Move the sub-driver unregistering up before the remove() calls shutdown(). But take a device ref on the idxd->conf_dev so that the memory does not get freed in ->release(). When all cleanup activities has been done, release the ref to allow the idxd memory to be freed. [57159.542766] RIP: 0010:ioread32+0x27/0x60 [57159.547097] Code: 00 66 90 48 81 ff ff ff 03 00 77 1e 48 81 ff 00 00 01 00 76 05 0f b7 d7 ed c3 8b 15 03 50 41 01 b8 ff ff ff ff 85 d2 75 04 c3 <8b> 07 c3 55 83 ea 01 48 89 fe 48 c7 c7 00 70 5f 82 48 89 e5 48 83 [57159.566647] RSP: 0018:ffffc900011abb60 EFLAGS: 00010292 [57159.572295] RAX: ffffc900011e0000 RBX: ffff888107d39800 RCX: 0000000000000000 [57159.579842] RDX: 0000000000000000 RSI: ffffffff82b1e448 RDI: ffffc900011e0090 [57159.587421] RBP: ffffc900011abb88 R08: 0000000000000000 R09: 0000000000000001 [57159.594972] R10: 0000000000000001 R11: 0000000000000000 R12: ffff8881019840d0 [57159.602533] R13: ffff8881097e9000 R14: ffffffffa08542a0 R15: 00000000000003a8 [57159.610093] FS: 00007f991e0a8740(0000) GS:ffff888459900000(0000) knlGS:00000000000 00000 [57159.618614] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [57159.624814] CR2: ffffc900011e0090 CR3: 000000010862a002 CR4: 00000000003706e0 [57159.632397] DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000 [57159.639973] DR3: 0000000000000000 DR6: 00000000fffe0ff0 DR7: 0000000000000400 [57159.647601] Call Trace: [57159.650502] ? idxd_device_disable+0x41/0x110 [idxd] [57159.655948] idxd_device_drv_remove+0x2b/0x80 [idxd] [57159.661374] idxd_config_bus_remove+0x16/0x20 [57159.666191] __device_release_driver+0x163/0x240 [57159.671320] device_release_driver+0x2b/0x40 [57159.676052] bus_remove_device+0xf5/0x160 [57159.680524] device_del+0x19c/0x400 [57159.684440] device_unregister+0x18/0x60 [57159.688792] idxd_remove+0x140/0x1c0 [idxd] [57159.693406] pci_device_remove+0x3e/0xb0 [57159.697758] __device_release_driver+0x163/0x240 [57159.702788] device_driver_detach+0x43/0xb0 [57159.707424] unbind_store+0x11e/0x130 [57159.711537] drv_attr_store+0x24/0x30 [57159.715646] sysfs_kf_write+0x4b/0x60 [57159.719710] kernfs_fop_write_iter+0x153/0x1e0 [57159.724563] new_sync_write+0x120/0x1b0 [57159.728812] vfs_write+0x23e/0x350 [57159.732624] ksys_write+0x70/0xf0 [57159.736335] __x64_sys_write+0x1a/0x20 [57159.740492] do_syscall_64+0x3b/0x90 [57159.744465] entry_SYSCALL_64_after_hwframe+0x44/0xae [57159.749908] RIP: 0033:0x7f991e19c387 [57159.753898] Code: 0d 00 f7 d8 64 89 02 48 c7 c0 ff ff ff ff eb b7 0f 1f 00 f3 0f 1e fa 64 8b 04 25 18 00 00 00 85 c0 75 10 b8 01 00 00 00 0f 05 <48> 3d 00 f0 ff ff 77 51 c3 48 83 ec 28 48 89 54 24 18 48 89 74 24 [57159.773564] RSP: 002b:00007ffc2ce2d6a8 EFLAGS: 00000246 ORIG_RAX: 0000000000000001 [57159.781550] RAX: ffffffffffffffda RBX: 000000000000000c RCX: 00007f991e19c387 [57159.789133] RDX: 000000000000000c RSI: 000055ee2630e140 RDI: 0000000000000001 [57159.796695] RBP: 000055ee2630e140 R08: 0000000000000000 R09: 00007f991e2324e0 [57159.804246] R10: 00007f991e2323e0 R11: 0000000000000246 R12: 000000000000000c [57159.811800] R13: 00007f991e26f520 R14: 000000000000000c R15: 00007f991e26f700 [57159.819373] Modules linked in: idxd bridge stp llc bnep sunrpc nls_iso8859_1 intel_ rapl_msr intel_rapl_common x86_pkg_temp_thermal intel_powerclamp coretemp snd_hda_code c_realtek iTCO_wdt 8250_dw snd_hda_codec_generic kvm_intel ledtrig_audio iTCO_vendor_s upport snd_hda_intel snd_intel_dspcfg ppdev kvm snd_hda_codec intel_wmi_thunderbolt sn d_hwdep irqbypass iwlwifi btusb snd_hda_core rapl btrtl intel_cstate snd_seq btbcm snd _seq_device btintel snd_pcm cfg80211 bluetooth pcspkr psmouse input_leds snd_timer int el_lpss_pci mei_me intel_lpss snd ecdh_generic ecc mei ucsi_acpi i2c_i801 idma64 i2c_s mbus virt_dma soundcore typec_ucsi typec wmi parport_pc parport video mac_hid acpi_pad sch_fq_codel drm ip_tables x_tables crct10dif_pclmul crc32_pclmul ghash_clmulni_intel usbkbd hid_generic usbmouse aesni_intel usbhid crypto_simd cryptd e1000e hid serio_ra w ahci libahci pinctrl_sunrisepoint fuse msr autofs4 [last unloaded: idxd] [57159.904082] CR2: ffffc900011e0090 [57159.907877] ---[ end trace b4e32f49ce9176a4 ]--- Fixes: 49c4959f ("dmaengine: idxd: fix sequence for pci driver remove() and shutdown()") Reported-by:
Ziye Yang <ziye.yang@intel.com> Signed-off-by:
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Dave Jiang authored
Remove setting of wq type on guest kernel during configuration load on RO device config. The user will set the kernel wq type and this setting based on config is not necessary. Signed-off-by:
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Dongliang Mu authored
Since pm_runtime_put is done when tegra_adma_probe is successful, we cannot do pm_runtime_put_sync again in tegra_adma_remove. Fix this by removing the pm_runtime_put_sync in tegra_adma_remove. Signed-off-by:
Dongliang Mu <mudongliangabcd@gmail.com> Reviewed-by:
Jon Hunter <jonathanh@nvidia.com> Link: https://lore.kernel.org/r/20211021031432.3466261-1-mudongliangabcd@gmail.comSigned-off-by:
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Dongliang Mu authored
The previous commit 059e969c ("dmaengine: tegra210-adma: Using pm_runtime_resume_and_get to replace open coding") forgets to replace the pm_runtime_get_sync in the tegra_adma_probe, but removes the pm_runtime_put_noidle. Fix this by continuing to replace pm_runtime_get_sync with pm_runtime_resume_and_get in tegra_adma_probe. Fixes: 059e969c ("dmaengine: tegra210-adma: Using pm_runtime_resume_and_get to replace open coding") Signed-off-by:
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Dongliang Mu authored
In rcar_dmac_probe, if pm_runtime_resume_and_get fails, it forgets to disable runtime PM. And of_dma_controller_free should only be invoked after the success of of_dma_controller_register. Fix this by refactoring the error handling code. Signed-off-by:
Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20211020143546.3436205-1-mudongliangabcd@gmail.comSigned-off-by:
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Lars-Peter Clausen authored
Before the `callback_result` callback was introduced drivers coded their invocation to the callback in a similar way to: if (cb->callback) { spin_unlock(&dma->lock); cb->callback(cb->callback_param); spin_lock(&dma->lock); } With the introduction of `callback_result` two helpers where introduced to transparently handle both types of callbacks. And drivers where updated to look like this: if (dmaengine_desc_callback_valid(cb)) { spin_unlock(&dma->lock); dmaengine_desc_callback_invoke(cb, ...); spin_lock(&dma->lock); } dmaengine_desc_callback_invoke() correctly handles both `callback_result` and `callback`. But we forgot to update the dmaengine_desc_callback_valid() function to check for `callback_result`. As a result DMA descriptors that use the `callback_result` rather than `callback` don't have their callback invoked by drivers that follow the pattern above. Fix this by checking for both `callback` and `callback_result` in dmaengine_desc_callback_valid(). Fixes: f067025b ("dmaengine: add support to provide error result from a DMA transation") Signed-off-by:Lars-Peter Clausen <lars@metafoo.de> Acked-by:
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- 18 Oct, 2021 24 commits
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Flavio Suligoi authored
Space prohibited between function name and open parenthesis '(' Signed-off-by:Flavio Suligoi <f.suligoi@asem.it> Link: https://lore.kernel.org/r/20210928151833.589843-4-f.suligoi@asem.itSigned-off-by:
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Flavio Suligoi authored
Alignment should match open parenthesis. Signed-off-by:
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Flavio Suligoi authored
The "if" conditional statement is not a single statement, so both branches require braces. Signed-off-by:
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Flavio Suligoi authored
Braces {} are not necessary for single statement blocks. Signed-off-by: -
Pandith N authored
Add support for setting dma coherent mask, dma mask is set to 64 bit Signed-off-by:
Pandith N <pandith.n@intel.com> Reviewed-by:
Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20211001140812.24977-4-pandith.n@intel.comSigned-off-by:
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Pandith N authored
Added hardware handshake selection in channel config, for mem2per and per2mem case. The peripheral specific handshake interface needs to be programmed in src_per, dst_per bits of CHx_CFG register. Signed-off-by:
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Pandith N authored
Added support for DMA controller with more than 8 channels. DMAC register map changes based on number of channels. Enabling DMAC channel: DMAC_CHENREG has to be used when number of channels <= 8 DMAC_CHENREG2 has to be used when number of channels > 8 Configuring DMA channel: CHx_CFG has to be used when number of channels <= 8 CHx_CFG2 has to be used when number of channels > 8 Suspending and resuming channel: DMAC_CHENREG has to be used when number of channels <= 8 DMAC_CHSUSPREG has to be used for suspending a channel > 8 Signed-off-by:
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Amelie Delaunay authored
Theorically, address pointers used by STM32 DMA must be chosen so as to ensure that all transfers within a burst block are aligned on the address boundary equal to the size of the transfer. If this is always the case for peripheral addresses on STM32, it is not for memory addresses if the user doesn't respect this alignment constraint. To avoid a weird behavior of the DMA controller in this case (no error triggered but data are not transferred as expected), force no burst. Signed-off-by:
Amelie Delaunay <amelie.delaunay@foss.st.com> Link: https://lore.kernel.org/r/20211011094259.315023-4-amelie.delaunay@foss.st.comSigned-off-by:
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Amelie Delaunay authored
buf_addr parameter of stm32_dma_set_xfer_param function is a dma_addr_t. We only need to check the remainder of buf_addr/max_width, so, no need to use do_div and extra u64 addr. Use '%' instead. Fixes: e0ebdbdc ("dmaengine: stm32-dma: take address into account when computing max width") Signed-off-by:
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Amelie Delaunay authored
To prevent accidental repeated completion, mark pending descriptor complete in terminate_all. It can be the case when terminate_all is called while no end of transfer interrupt occurs. Signed-off-by:
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Christophe JAILLET authored
'head' is unused, remove it. Signed-off-by:
Christophe JAILLET <christophe.jaillet@wanadoo.fr> Link: https://lore.kernel.org/r/46e071be21fbc5ac5c35d4796a7e4249e94c3a77.1633847306.git.christophe.jaillet@wanadoo.frSigned-off-by:
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Artur Rojek authored
Total amount of SG list entries executed in a single burst is limited by the number of available DMA descriptors. This information is useful for device drivers utilizing this DMA engine. Signed-off-by:
Artur Rojek <contact@artur-rojek.eu> Acked-by:
Paul Cercueil <paul@crapouillou.net> Link: https://lore.kernel.org/r/20210829195805.148964-1-contact@artur-rojek.euSigned-off-by:
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Biju Das authored
Currently, DMA clocks are turned on by the bootloader. This patch adds support for DMA clock handling so that the driver manages the DMA clocks. Fixes: 5000d370 ("dmaengine: sh: Add DMAC driver for RZ/G2L SoC") Signed-off-by:
Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by:
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Dave Jiang authored
Remove max_descs_per_engine field. The recently released DSA spec 1.2 [1] has removed this field and made it reserved. [1]: https://software.intel.com/content/dam/develop/external/us/en/documents-tps/341204-intel-data-streaming-accelerator-spec.pdfSigned-off-by:
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Dave Jiang authored
DSA spec 1.2 has moved the GENCFG register under the GENCAP configuration support with respect to writability. Add check in driver before writing to GENCFG register. Signed-off-by:
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Anatolij Gustschin authored
memset() and memcpy() on an MMIO region like here results in a lockup at startup on mpc5200 platform (since this first happens during probing of the ATA and Ethernet drivers). Use memset_io() and memcpy_toio() instead. Fixes: 2f9ea1bd ("bestcomm: core bestcomm support for Freescale MPC5200") Cc: stable@vger.kernel.org # v5.14+ Signed-off-by:
Anatolij Gustschin <agust@denx.de> Link: https://lore.kernel.org/r/20211014094012.21286-1-agust@denx.deSigned-off-by:
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Claudiu Beznea authored
Use pm_ptr() macro to fill at_xdmac_driver.driver.pm. Signed-off-by:
Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by:
Tudor Ambarus <tudor.ambarus@microchip.com> Link: https://lore.kernel.org/r/20211007111230.2331837-5-claudiu.beznea@microchip.comSigned-off-by:
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Claudiu Beznea authored
Use __maybe_unused for pm functions. Signed-off-by:
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Claudiu Beznea authored
AT_XDMAC_CC_PERID() should be used to setup bits 24..30 of XDMAC_CC register. Using it without parenthesis around 0x7f & (i) will lead to setting all the time zero for bits 24..30 of XDMAC_CC as the << operator has higher precedence over bitwise &. Thus, add paranthesis around 0x7f & (i). Fixes: 15a03850 ("dmaengine: at_xdmac: fix macro typo") Signed-off-by:
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Claudiu Beznea authored
at_xdmac could be used on SoCs which supports backup mode (where most of the SoC power, including power to DMA controller, is closed at suspend time). Thus, on resume, the settings which were previously done need to be restored. Do the same for axi configuration. Fixes: f40566f2 ("dmaengine: at_xdmac: add AXI priority support and recommended settings") Signed-off-by:
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Colin Ian King authored
The variable err is being initialized with a value that is never read, it is being updated later on. The assignment is redundant and can be removed and move the declaration into the local scope. Addresses-Coverity: ("Unused value") Signed-off-by:Colin Ian King <colin.king@canonical.com> Link: https://lore.kernel.org/r/20211015123447.27560-1-colin.king@canonical.comSigned-off-by:
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Sameer Pujar authored
ADMAIF FIFO uses a ring buffer and it is divided amongst the available channels. The default FIFO size (in multiples of 16 words) of ADMAIF TX/RX channels is as below: * On Tegra210, channel 1 to 2 : size = 3 channel 3 to 10: size = 2 * On Tegra186 and later, channel 1 to 4 : size = 3 channel 5 to 20: size = 2 As per recommendation from HW, FIFO size of ADMA channel should be same as the corresponding ADMAIF channel it maps to. FIFO corruption is observed if the sizes do not match. We are using the default FIFO sizes for ADMAIF and there is no plan to support any custom values. Thus at runtime, override the ADMA channel FIFO size value depending on the corresponding ADMAIF channel. Signed-off-by:Sameer Pujar <spujar@nvidia.com> Reviewed-by:
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Sameer Pujar authored
Trivial change to add description for 'adma_get_burst_config' in chip data structure. Signed-off-by:
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Sameer Pujar authored
The 'has_outstanding_reqs' member description order in structure 'tegra_adma_chip_data' does not match with the corresponding member declaration. The same is true for member assignment in chip data structures declared for Tegra210 and Tegra186. This is a trivial fix to re-order the mentioned member for a better readability. Signed-off-by:
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- 01 Oct, 2021 4 commits
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Dave Jiang authored
percpu_ref_tryget_live() is safe to call as long as ref is between init and exit according to the function comment. Move percpu_ref_exit() so it is called after the dma channel is no longer valid to ensure this holds true. Fixes: 93a40a6d ("dmaengine: idxd: add percpu_ref to descriptor submission path") Suggested-by:
Kevin Tian <kevin.tian@intel.com> Signed-off-by:
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Gustavo A. R. Silva authored
Make use of the struct_size() helper instead of an open-coded version, in order to avoid any potential type mistakes or integer overflows that, in the worse scenario, could lead to heap overflows. Link: https://github.com/KSPP/linux/issues/160Signed-off-by:
Gustavo A. R. Silva <gustavoars@kernel.org> Reviewed-by:
Kees Cook <keescook@chromium.org> Link: https://lore.kernel.org/r/20210929222922.GA357509@embeddedorSigned-off-by:
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Michael Tretter authored
The tasklet that handles the completed dma transfers uses spin_unlock for unlocking a spin lock that was previously locked with spin_lock_irqsave. This caused the following lockdep warning about an inconsistent lock state: inconsistent {HARDIRQ-ON-W} -> {IN-HARDIRQ-W} usage. We must use spin_lock_irqsave, because it is possible to queue DMA transfers from an irq handler. Replace the spin_unlock and spin_lock by spin_unlock_irqrestore and spin_lock_irqsave. Signed-off-by:Michael Tretter <m.tretter@pengutronix.de> Link: https://lore.kernel.org/r/20210826094742.1302009-8-m.tretter@pengutronix.deSigned-off-by:
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Michael Tretter authored
The descriptor lists are locked for the entire tasklet that completes the descriptors. This is not necessary, because the lock actually only protects the descriptor lists. Make the spin lock more fine-grained and only protect functions that actually operate on the descriptor lists. This decreases the time when the lock is held. Signed-off-by:
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