- 21 Sep, 2021 34 commits
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Stephan Gerhold authored
This fixes the following warning when building with W=1: Warning (unit_address_vs_reg): /soc: node has a reg or ranges property, but no unit name Signed-off-by:
Stephan Gerhold <stephan@gerhold.net> Reviewed-by:
Stephen Boyd <swboyd@chromium.org> Signed-off-by:
Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210921152120.6710-1-stephan@gerhold.net
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Stephen Boyd authored
Let's use the GIC_SPI macro instead of a plain 0 here to match other uses of the primary interrupt controller on sc7280. Suggested-by:
Matthias Kaehlcke <mka@chromium.org> Cc: Alex Elder <elder@linaro.org> Signed-off-by:
Alex Elder <elder@linaro.org> Signed-off-by:
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Manaf Meethalavalappu Pallikunhi authored
Add cooling-cells property and the cooling maps for the gpu thermal zones to support GPU thermal cooling. Signed-off-by:
Manaf Meethalavalappu Pallikunhi <manafm@codeaurora.org> Signed-off-by:
Akhil P Oommen <akhilpo@codeaurora.org> Reviewed-by:
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Akhil P Oommen authored
Add the necessary dt nodes for gpu support in sc7280. Signed-off-by:
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Taniya Das authored
Add the GPUCC, DISPCC and VIDEOCC clock headers which were dropped earlier. Signed-off-by:
Taniya Das <tdas@codeaurora.org> Reviewed-by:
Douglas Anderson <dianders@chromium.org> Signed-off-by:
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satya priya authored
Add pm7325 PMIC gpio support for vol+ on sc7280-idp. Signed-off-by:
satya priya <skakit@codeaurora.org> Reviewed-by:
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Dmitry Baryshkov authored
Enable powerkey and resin nodes to let the board handle POWER and Volume- keys properly. Signed-off-by:
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by:
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Dmitry Baryshkov authored
Specify recovery and bootloader magic values to be programmed by the qcom-pon driver. This allows the bootloader to handle reboot-to-bootloader functionality. Signed-off-by:
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Dmitry Baryshkov authored
Change pm8150 to use the qcom,pm8998-pon compatible string for the pon in order to pass reboot mode properly. Fixes: 5101f22a ("arm64: dts: qcom: pm8150: Add base dts file") Signed-off-by:
Amit Pundir <amit.pundir@linaro.org> Signed-off-by:
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Kathiravan T authored
Based on downstream codeaurora code. Tested (USB2 only) on IPQ6010 based hardware. Signed-off-by:
Kathiravan T <kathirav@codeaurora.org> Signed-off-by:
Baruch Siach <baruch@tkos.co.il> [bjorn: Changed dwc3 node name to usb, per binding] Signed-off-by:
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Shawn Guo authored
Follow dma-controller.yaml schema to use `dma-controller` as node name of BAM DMA devices. Signed-off-by:
Shawn Guo <shawn.guo@linaro.org> Signed-off-by:
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Douglas Anderson authored
There's nothing magical about GPIO91 and boards could use different GPIOs for card detect. Move the pin out of the dtsi file and to the only existing board file. Signed-off-by:
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Shawn Guo authored
Property qcom,controlled-remotely should be boolean. Fix it. Signed-off-by:
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Shawn Guo authored
Property qcom,controlled-remotely should be boolean. Fix it. Signed-off-by:
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Shawn Guo authored
Property qcom,controlled-remotely should be boolean. Fix it. Signed-off-by:
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Rajendra Nayak authored
sc7280 has 8 big.LITTLE CPUs setup with DynamIQ, so all cores are within the same CPU cluster. Add cpu-map to define the CPU topology. Signed-off-by:
Rajendra Nayak <rnayak@codeaurora.org> Reviewed-by:
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Bjorn Andersson authored
The firmware for the modem and WiFi subsystems platform specific and is signed with a OEM specific key (or a test key). In order to support more than a single device it is therefor not possible to rely on the default path and stash these files directly in the firmware directory. This has already been addressed for other platforms, but the APQ8016 SBC (aka db410c) was never finished upstream. Signed-off-by:
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Steev Klimaszewski authored
On the Lenovo Yoga C630, the WiFi/BT chip can use both RF channels/antennas, so add the regulator for it. Signed-off-by:
Steev Klimaszewski <steev@kali.org> Signed-off-by:
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Kuogee Hsieh authored
Existing display port phy reg property is derived from usb phy which map display port phy pcs to wrong address which cause aux init with wrong address and prevent both dpcd read and write from working. Fix this problem by assigning correct pcs address to display port phy reg property. Fixes: bb9efa59 ("arm64: dts: qcom: sc7280: Add USB related nodes") Signed-off-by:
Kuogee Hsieh <khsieh@codeaurora.org> Reviewed-by:
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Matthias Kaehlcke authored
Homestar is a trogdor variant. The DT bits are essentially the same as in the downstream tree, except for: - skip -rev0 and rev1 which were early builds and have their issues, it's not very useful to support them upstream - don't include the .dtsi for the MIPI cameras, which doesn't exist upstream Signed-off-by:
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Robert Marko authored
IPQ8074 uses SPMI for communication with the PMIC, so since its already supported add the DT node for it. Signed-off-by:
Robert Marko <robimarko@gmail.com> Signed-off-by:
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AngeloGioacchino Del Regno authored
The PMI8998 PMIC has a WLED backlight controller, which is used on most MSM8998 and SDM845 based devices: add a base configuration for it and keep it disabled. This contains only the PMIC specific configuration that does not change across boards; parameters like number of strings, OVP and current limits are product specific and shall be specified in the product DT in order to achieve functionality. Signed-off-by:
AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Signed-off-by:
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Matthias Kaehlcke authored
The charger thermistor on Lazor, CoachZ rev1 and Pompom rev1+2 is either the wrong part or not stuffed at all, the same is true for the skin temperature thermistor on CoachZ rev1. The corresponding thermal zones are already disabled for these devices, in addition delete the ADC nodes of the thermistors. For Lazor and CoachZ rev1 also disable the PM6150 ADC and thermal monitor since none of the ADC channels is used. Signed-off-by:
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Robert Marko authored
tx-fifo-resize is now added by default by the dwc3-qcom driver to the SNPS DWC3 child node. So, lets drop the tx-fifo-resize property from dwc3-qcom nodes as having it there will cause the dwc3-qcom driver to error and abort probe with: [ 1.362938] dwc3-qcom 8af8800.usb: unable to add property [ 1.368405] dwc3-qcom 8af8800.usb: failed to register DWC3 Core, err=-17 Fixes: cefdd52f ("usb: dwc3: dwc3-qcom: Enable tx-fifo-resize property by default") Signed-off-by:
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Douglas Anderson authored
The sc7180's dynamic-power-coefficient violates the device tree bindings. The bindings (arm/cpus.yaml) say that the units for the dynamic-power-coefficient are supposed to be "uW/MHz/V^2". The ones for sc7180 aren't this. Qualcomm arbitrarily picked 100 for the "little" CPUs and then picked a number for the big CPU based on this. At the time, there was a giant dicussion about this. Apparently Qualcomm Engineers were instructed not to share the actual numbers here. As part of the discussion, I pointed out [1] that these numbers shouldn't really be secret since once a device is shipping anyone can just run a script and produce them. This patch is the result of running the script I posted in that discussion on sc7180-trogdor-coachz, which is currently available for purchase by consumers. [1] https://lore.kernel.org/r/CAD=FV=U1FP0e3_AVHpauUUZtD-5X3XCwh5aT9fH_8S_FFML2Uw@mail.gmail.com/ I ran the script four times, measuring little, big, little, big. I used the 64-bit version of dhrystone 2.2 in my test. I got these results: 576 kHz, 596 mV, 20 mW, 88 Cx 768 kHz, 596 mV, 32 mW, 122 Cx 1017 kHz, 660 mV, 45 mW, 97 Cx 1248 kHz, 720 mV, 87 mW, 139 Cx 1324 kHz, 756 mV, 109 mW, 148 Cx 1516 kHz, 828 mV, 150 mW, 148 Cx 1612 kHz, 884 mV, 182 mW, 147 Cx 1708 kHz, 884 mV, 192 mW, 146 Cx 1804 kHz, 884 mV, 207 mW, 149 Cx Your dynamic-power-coefficient for cpu 0: 132 825 kHz, 596 mV, 142 mW, 401 Cx 979 kHz, 628 mV, 183 mW, 427 Cx 1113 kHz, 656 mV, 224 mW, 433 Cx 1267 kHz, 688 mV, 282 mW, 449 Cx 1555 kHz, 812 mV, 475 mW, 450 Cx 1708 kHz, 828 mV, 566 mW, 478 Cx 1843 kHz, 884 mV, 692 mW, 476 Cx 1900 kHz, 884 mV, 722 mW, 482 Cx 1996 kHz, 916 mV, 814 mW, 482 Cx 2112 kHz, 916 mV, 862 mW, 483 Cx 2208 kHz, 916 mV, 962 mW, 521 Cx 2323 kHz, 940 mV, 1060 mW, 517 Cx 2400 kHz, 956 mV, 1133 mW, 518 Cx Your dynamic-power-coefficient for cpu 6: 471 576 kHz, 596 mV, 26 mW, 103 Cx 768 kHz, 596 mV, 40 mW, 147 Cx 1017 kHz, 660 mV, 54 mW, 114 Cx 1248 kHz, 720 mV, 97 mW, 151 Cx 1324 kHz, 756 mV, 113 mW, 150 Cx 1516 kHz, 828 mV, 154 mW, 148 Cx 1612 kHz, 884 mV, 194 mW, 155 Cx 1708 kHz, 884 mV, 203 mW, 152 Cx 1804 kHz, 884 mV, 219 mW, 155 Cx Your dynamic-power-coefficient for cpu 0: 142 825 kHz, 596 mV, 148 mW, 530 Cx 979 kHz, 628 mV, 189 mW, 475 Cx 1113 kHz, 656 mV, 230 mW, 461 Cx 1267 kHz, 688 mV, 287 mW, 466 Cx 1555 kHz, 812 mV, 469 mW, 445 Cx 1708 kHz, 828 mV, 567 mW, 480 Cx 1843 kHz, 884 mV, 699 mW, 482 Cx 1900 kHz, 884 mV, 719 mW, 480 Cx 1996 kHz, 916 mV, 814 mW, 484 Cx 2112 kHz, 916 mV, 861 mW, 483 Cx 2208 kHz, 916 mV, 963 mW, 522 Cx 2323 kHz, 940 mV, 1063 mW, 520 Cx 2400 kHz, 956 mV, 1135 mW, 519 Cx Your dynamic-power-coefficient for cpu 6: 489 As you can see, the calculations aren't perfectly consistent but roughly you could say about 480 for big and 137 for little. The ratio between these numbers isn't quite the same as the ratio between the two numbers that Qualcomm used. Perhaps this is because Qualcomm measured something slightly different than the 64-bit version of dhrystone 2.2 or perhaps it's because they fudged these numbers a bit (and fudged the capacity-dmips-mhz). As per discussion [2], let's use the numbers I came up with and also un-fudge capacity-dmips-mhz. While unfudging capacity-dmips-mhz, let's scale it so that bigs are 1024 which seems to be the common practice. In general these numbers don't need to be perfectly exact. In fact, they can't be since the CPU power depends a lot on what's being run on the CPU and the big/little CPUs are each more or less efficient in different operations. Historically running the 32-bit vs. 64-bit versions of dhrystone produced notably different numbers, though I didn't test this time. We also need to scale all of the sustainable-power numbers by the same amount. I scale ones related to the big CPUs by the adjustment I made to the big dynamic-power-coefficient and the ones related to the little CPUs by the adjustment I made to the little dynamic-power-coefficient. [2] https://lore.kernel.org/r/0a865b6e-be34-6371-f9f2-9913ee1c5608@codeaurora.org/ Fixes: 71f87316 ("arm64: dts: qcom: sc7180: Add dynamic CPU power coefficients") Signed-off-by:
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Raffaele Tranquillini authored
Add a device tree for Xiaomi Mi 5 (gemini). Signed-off-by:
Raffaele Tranquillini <raffaele.tranquillini@gmail.com> Signed-off-by:
Yassine Oudjana <y.oudjana@protonmail.com> Signed-off-by:
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Yassine Oudjana authored
There are 5 Xiaomi devices with the MSM8996 SoC: - Mi 5 (gemini): MSM8996 + PMI8994 - Mi Note 2 (scorpio): MSM8996 Pro + PMI8996 - Mi 5s (capricorn): MSM8996 Pro + PMI8996 - Mi Mix (lithium): MSM8996 Pro + PMI8996 - Mi 5s Plus (natrium): MSM8996 Pro + PMI8996 These devices share a common board design with only a few differences. Add support for the common board, as well as support for the Mi Note 2. Signed-off-by:
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Yassine Oudjana authored
Add a node for blsp2_i2c3 which is used for type-C port control chips and speaker codecs on some devices. Signed-off-by:
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Yassine Oudjana authored
Move blsp1_uart2_default and blsp1_uart2_sleep to the SoC device tree to avoid duplicating them in other device trees. Signed-off-by:
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AngeloGioacchino Del Regno authored
The MSM8998 SoC includes an Adreno 540.1 GPU, with a maximum frequency of 710MHz. This GPU may or may not accept a ZAP shader, depending on platform configuration, so adding a zap-shader node is left to the board DT. Signed-off-by:
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AngeloGioacchino Del Regno authored
The QFPROM iospace was (erroneously, I believe) set to the uncalibrated fuse start address, but every driver only needs - and will always only need - only calibrated values. Move the iospace forward to the calibrated values start to avoid offsetting every fuse definition. Obviously, the only defined fuse (qusb2_hstx_trim) was also fixed to remove the offset, in order to comply with this change. Signed-off-by:
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AngeloGioacchino Del Regno authored
The entry/exit latency and minimum residency in state for the idle states of MSM8998 were ..bad: first of all, for all of them the timings were written for CPU sleep but the min-residency-us param was miscalculated (supposedly, while porting this from downstream); Then, the power collapse states are setting PC on both the CPU cluster *and* the L2 cache, which have different timings: in the specific case of L2 the times are higher so these ones should be taken into account instead of the CPU ones. This parameter misconfiguration was not giving particular issues because on MSM8998 there was no CPU scaling at all, so cluster/L2 power collapse was rarely (if ever) hit. When CPU scaling is enabled, though, the wrong timings will produce SoC unstability shown to the user as random, apparently error-less, sudden reboots and/or lockups. This set of parameters are stabilizing the SoC when CPU scaling is ON and when power collapse is frequently hit. Signed-off-by:
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AngeloGioacchino Del Regno authored
In preparation for enabling various components of the multimedia subsystem, write configuration for its related IOMMU. Signed-off-by:
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AngeloGioacchino Del Regno authored
The MSM8998 MMCC is supported and has a driver: configure it as a preparation for a later enablement of multimedia nodes (mdp, venus and others). Signed-off-by:
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- 15 Sep, 2021 4 commits
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Thara Gopinath authored
Now that Limits h/w is enabled to monitor thermal events around cpus and throttle the cpu frequencies, remove cpufreq cooling device for the CPU thermal zones which does software throttling of cpu frequencies. Reviewed-by:
Thara Gopinath <thara.gopinath@linaro.org> Signed-off-by:
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Thara Gopinath authored
Add LMh nodes for CPU cluster0 and CPU cluster1. Also add interrupt support in cpufreq node to capture the LMh interrupt and let the scheduler know of the max frequency throttling. Reviewed-by:
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Rajendra Nayak authored
Add vcc-supply for the IDP boards that was missed when the qfprom device tree properties were added for the sc7280 SoC. Fixes: c1b2189a ("arm64: dts: qcom: sc7280: Add qfprom node") Reported-by:
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Marijn Suijten authored
In a future patch the GCC driver will stop requesting this xo clock by its global "xo" name, in favour of having an explicit phandle here in the DT. Aside from that this clock in addition to the mandatory "sleep_clk" were never passed despite being required by the relevant dt-bindings. Reviewed-by:
Marijn Suijten <marijn.suijten@somainline.org> Signed-off-by:
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- 13 Sep, 2021 1 commit
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Bhupesh Sharma authored
In commit 3e482859 ("dts: qcom: sdm845: Add dt entries to support crypto engine."), we decided to use the value indicated by constant RPMH_CE_CLK rather than using it directly. Now that the same RPMH clock value might be used for other SoCs (in addition to sdm845), let's use the constant RPMH_CE_CLK to make sure that this dtsi is compatible with the other qcom ones. Signed-off-by:
Bhupesh Sharma <bhupesh.sharma@linaro.org> Reviewed-by:
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- 12 Sep, 2021 1 commit
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Linus Torvalds authored
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