- 21 Apr, 2021 10 commits
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Anthony Wang authored
[Why & How] We want to immediately fail seamless boot validation if DSC is active, as VBIOS currently does not support DSC timings. Add a check for the relevant flag in dc_validate_seamless_boot_timing. Signed-off-by:
Anthony Wang <anthony1.wang@amd.com> Reviewed-by:
Martin Leung <Martin.Leung@amd.com> Acked-by:
Aurabindo Pillai <aurabindo.pillai@amd.com> Tested-by:
Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Robin Singh authored
[why] During dsc enable, a divide by zero condition triggered the kernel crash. [how] An IGT test, which enable the DSC, was crashing at the time of restore the default dsc status, becaue of h_totals value becoming 0. So add a check before divide condition. If h_total is zero, gracefully ignore and set the default value. kernel panic log: [ 128.758827] divide error: 0000 [#1] PREEMPT SMP NOPTI [ 128.762714] CPU: 5 PID: 4562 Comm: amd_dp_dsc Tainted: G W 5.4.19-android-x86_64 #1 [ 128.769728] Hardware name: ADVANCED MICRO DEVICES, INC. Mauna/Mauna, BIOS WMN0B13N Nov 11 2020 [ 128.777695] RIP: 0010:hubp2_vready_at_or_After_vsync+0x37/0x7a [amdgpu] [ 128.785707] Code: 80 02 00 00 48 89 f3 48 8b 7f 08 b ...... [ 128.805696] RSP: 0018:ffffad8f82d43628 EFLAGS: 00010246 ...... [ 128.857707] CR2: 00007106d8465000 CR3: 0000000426530000 CR4: 0000000000140ee0 [ 128.865695] Call Trace: [ 128.869712] hubp3_setup+0x1f/0x7f [amdgpu] [ 128.873705] dcn20_update_dchubp_dpp+0xc8/0x54a [amdgpu] [ 128.877706] dcn20_program_front_end_for_ctx+0x31d/0x463 [amdgpu] [ 128.885706] dc_commit_state+0x3d2/0x658 [amdgpu] [ 128.889707] amdgpu_dm_atomic_commit_tail+0x4b3/0x1e7c [amdgpu] [ 128.897699] ? dm_read_reg_func+0x41/0xb5 [amdgpu] [ 128.901707] ? dm_read_reg_func+0x41/0xb5 [amdgpu] [ 128.905706] ? __is_insn_slot_addr+0x43/0x48 [ 128.909706] ? fill_plane_buffer_attributes+0x29e/0x3dc [amdgpu] [ 128.917705] ? dm_plane_helper_prepare_fb+0x255/0x284 [amdgpu] [ 128.921700] ? usleep_range+0x7c/0x7c [ 128.925705] ? preempt_count_sub+0xf/0x18 [ 128.929706] ? _raw_spin_unlock_irq+0x13/0x24 [ 128.933732] ? __wait_for_common+0x11e/0x18f [ 128.937705] ? _raw_spin_unlock_irq+0x13/0x24 [ 128.941706] ? __wait_for_common+0x11e/0x18f [ 128.945705] commit_tail+0x8b/0xd2 [drm_kms_helper] [ 128.949707] drm_atomic_helper_commit+0xd8/0xf5 [drm_kms_helper] [ 128.957706] amdgpu_dm_atomic_commit+0x337/0x360 [amdgpu] [ 128.961705] ? drm_atomic_check_only+0x543/0x68d [drm] [ 128.969705] ? drm_atomic_set_property+0x760/0x7af [drm] [ 128.973704] ? drm_mode_atomic_ioctl+0x6f3/0x85a [drm] [ 128.977705] drm_mode_atomic_ioctl+0x6f3/0x85a [drm] [ 128.985705] ? drm_atomic_set_property+0x7af/0x7af [drm] [ 128.989706] drm_ioctl_kernel+0x82/0xda [drm] [ 128.993706] drm_ioctl+0x225/0x319 [drm] [ 128.997707] ? drm_atomic_set_property+0x7af/0x7af [drm] [ 129.001706] ? preempt_count_sub+0xf/0x18 [ 129.005713] amdgpu_drm_ioctl+0x4b/0x76 [amdgpu] [ 129.009705] vfs_ioctl+0x1d/0x2a [ 129.013705] do_vfs_ioctl+0x419/0x43d [ 129.017707] ksys_ioctl+0x52/0x71 [ 129.021707] __x64_sys_ioctl+0x16/0x19 [ 129.025706] do_syscall_64+0x78/0x85 [ 129.029705] entry_SYSCALL_64_after_hwframe+0x44/0xa9 Signed-off-by:
Robin Singh <robin.singh@amd.com> Reviewed-by:
Harry Wentland <Harry.Wentland@amd.com> Reviewed-by:
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Jiansong Chen authored
dimgrey_cavefish has similar gc_10_3 ip with sienna_cichlid, so follow its registers offset setting. Signed-off-by:
Jiansong Chen <Jiansong.Chen@amd.com> Reviewed-by:
Tao Zhou <tao.zhou1@amd.com> Signed-off-by:
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John Clements authored
resolve bug on aldebaran where gfx error counts will print on driver load when there are no errors present Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
John Clements <john.clements@amd.com> Signed-off-by:
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Dennis Li authored
because "sscanf(str, "retire_page")" always return 0, if application use the raw data for error injection, it always wrongly falls into "op == 3". Change to use strstr instead. Signed-off-by:
Dennis Li <Dennis.Li@amd.com> Reviewed-by:
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Hawking Zhang authored
In aldebaran, driver only needs to harvest SDP RdRspStatus, WrRspStatus and first parity error on RdRsp data. Check error type before harvest error information. Signed-off-by:
Stanley Yang <Stanley.Yang@amd.com> Signed-off-by:
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Hawking Zhang authored
SDP RdRspStatus/WrRspStatus or first parity error on RdRsp data can cause system fatal error in arcturus. GPU will be freezed in such case. Driver needs to harvest these error information before reset the GPU. Check error type to avoid harvest normal gcea/mmea information. Signed-off-by:
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Huang Rui authored
The tmz functions are verified on renoir chips as well. So enable it by default. Signed-off-by:
Huang Rui <ray.huang@amd.com> Tested-by:
Lang Yu <Lang.Yu@amd.com> Reviewed-by:
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Hawking Zhang authored
When gfx wdt was configured to fatal_disable, the timeout period should be configured to 0x0 (timeout disabled) Signed-off-by:
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Dennis Li authored
In poison progogate mode, when driver receive the edc error interrupt from SQ, driver should kill the process by pasid which is using the poison data, and then trigger GPU reset. Signed-off-by:
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- 15 Apr, 2021 30 commits
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Yang Li authored
Kernel test robot throws below warning -> smatch warnings: drivers/gpu/drm/radeon/si.c:4514 si_vm_packet3_cp_dma_check() warn: inconsistent indenting Fixed the inconsistent indenting. Reported-by:
Abaci Robot <abaci@linux.alibaba.com> Signed-off-by:
Yang Li <yang.lee@linux.alibaba.com> Signed-off-by:
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Dan Carpenter authored
We should return -EINVAL instead of success if the "limit" is too high. Fixes: e098bc96 ("drm/amd/pm: optimize the power related source code layout") Signed-off-by:
Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by:
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Dan Carpenter authored
If the kmemdup() fails then this should return a negative error code but it currently returns success Fixes: b4a7db71 ("drm/amdgpu: add per device user friendly xgmi events for vega20") Signed-off-by:
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Tian Tao authored
The value of pipe_id and queue_id are not used under certain circumstances, so just delete. Signed-off-by:
Tian Tao <tiantao6@hisilicon.com> Signed-off-by:
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Simon Ser authored
Accept non-linear buffers which use a multi-planar format, as long as they don't use DCC. Tested on GFX9 with NV12. Signed-off-by:
Simon Ser <contact@emersion.fr> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: Harry Wentland <hwentlan@amd.com> Cc: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Cc: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Reviewed-by:
Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Signed-off-by:
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Shashank Sharma authored
This patch checks the return value of the function dc_link_add_remote_sink before using it. This was causing a crash during consecutive hotplugs of DP MST displays. Cc: Harry Wentland <harry.wentland@amd.com> Reviewed-by:
Shashank Sharma <shashank.sharma@amd.com> Signed-off-by:
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Qingqing Zhuo authored
This reverts commit 55fa622f. The regression caused by the original patch has been cleared, thus introduce back the change. Signed-off-by:
Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by:
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Qingqing Zhuo authored
[Why] Current list supports modifiers that have DCC_MAX_COMPRESSED_BLOCK set to AMD_FMT_MOD_DCC_BLOCK_128B, while AMD_FMT_MOD_DCC_BLOCK_64B is used instead by userspace. [How] Replace AMD_FMT_MOD_DCC_BLOCK_128B with AMD_FMT_MOD_DCC_BLOCK_64B for modifiers with DCC supported. Fixes: faa37f54 ("drm/amd/display: Expose modifiers") Signed-off-by:
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Xiaojian Du authored
This patch is to revise two names of sensor values for vangogh. New smu metrics table is supported by new pmfw (from version 4.63.36.00 ), it includes two parts, one part is the current smu metrics table data and the other part is the average smu metrics table data. The hwmon will read the current gfxclk and mclk from the current smu metrics table data. Signed-off-by:
Xiaojian Du <Xiaojian.Du@amd.com> Reviewed-by:
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Xiaojian Du authored
This patch is to remove the "set" function of pp_dpm_mclk for vangogh. For vangogh, mclk bonds with fclk, they will lock each other on the same perfomance level. But according to the smu message from pmfw, only fclk is allowed to set value manually, so remove the unnecessary code of "set" function for mclk. Signed-off-by:
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Joseph Greathouse authored
If we skipped loading MEC2 firmware separately from MEC, then MEC2 will be running the same firmware image. Copy the MEC version and feature numbers into MEC2 version and feature numbers. This is needed for things like GWS support, where we rely on knowing what version of firmware is running on MEC2. Leaving these MEC2 entries blank breaks our ability to version-check enables and workarounds. Signed-off-by:
Joseph Greathouse <Joseph.Greathouse@amd.com> Reviewed-by:
Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by:
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Xiaojian Du authored
This patch is to add the callback to get the bootup values for renoir. Signed-off-by:
Lijo Lazar <lijo.lazar@amd.com> Acked-by:
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Xiaojian Du authored
This patch is to update the atomfirmware header for smu12. v2: remove some unnecessary members Signed-off-by:
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Felix Kuehling authored
ROCm user mode has acquired VMs from DRM file descriptors for as long as it supported the upstream KFD. Legacy code to support older versions of ROCm is not needed any more. Signed-off-by:
Philip Yang <Philip.Yang@amd.com> Signed-off-by:
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Ramesh Errabolu authored
drm/amdgpu: Use iterator methods exposed by amdgpu_res_cursor.h in building SG_TABLE's for a VRAM BO Extend current implementation of SG_TABLE construction method to allow exportation of sub-buffers of a VRAM BO. This capability will enable logical partitioning of a VRAM BO into multiple non-overlapping sub-buffers. One example of this use case is to partition a VRAM BO into two sub-buffers, one for SRC and another for DST. Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
Ramesh Errabolu <Ramesh.Errabolu@amd.com> Signed-off-by:
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Luben Tuikov authored
Add back the double-sscanf so that both decimal and hexadecimal values could be read in, but this time invert the scan so that hexadecimal format with a leading 0x is tried first, and if that fails, then try decimal format. Also use a logical-AND instead of nesting double if-conditional. See commit "drm/amdgpu: Fix a bug for input with double sscanf" Cc: Alexander Deucher <Alexander.Deucher@amd.com> Cc: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
Luben Tuikov <luben.tuikov@amd.com> Reviewed-by:
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Kenneth Feng authored
add ASPM support on polaris Signed-off-by:
Kenneth Feng <kenneth.feng@amd.com> Reviewed-by:
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Kenneth Feng authored
enable ASPM on vega to save the power without the performance hurt. Signed-off-by:
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Kenneth Feng authored
enable ASPM on navi1x for the benifit of system power consumption without performance hurt. Signed-off-by:
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Jack Zhang authored
No need to config GECC feature here for sriov Leave the host drvier to do the configuration job. Signed-off-by:
Jack Zhang <Jack.Zhang1@amd.com> Reviewed-by:
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Lijo Lazar authored
When GFXCLK range is updated in manual/determinism mode, show the updated min/max clock range. Signed-off-by:
Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com> Signed-off-by:
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Luben Tuikov authored
Imporve the kernel-doc for the RAS sysfs interface. Fix the grammar, fix the context. Cc: Alexander Deucher <Alexander.Deucher@amd.com> Cc: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
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Luben Tuikov authored
Add bad_page_cnt_threshold to debugfs, an optional file system used for debugging, for reporting purposes only--it usually matches the size of EEPROM but may be different depending on the "bad_page_threshold" kernel module option. The "bad_page_cnt_threshold" is a dynamically computed value. It depends on three things: the VRAM size; the size of the EEPROM (or the size allocated to the RAS table therein); and the "bad_page_threshold" module parameter. It is a dynamically computed value, when the amdgpu module is run, on which further parameters and logic depend, and as such it is helpful to see the dynamically computed value in debugfs. Cc: Alexander Deucher <Alexander.Deucher@amd.com> Cc: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
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Luben Tuikov authored
Fix if (ret) --> if (!ret), a bug, for "retire_page", which caused the kernel to recall the method with *pos == end of file, and that bounced back with error. On the first run, we advanced *pos, but returned 0 back to fs layer, also a bug. Fix the logic of the check of the result of amdgpu_reserve_page_direct()--it is 0 on success, and non-zero on error, not the other way around. This patch fixes this bug. Cc: Alexander Deucher <Alexander.Deucher@amd.com> Cc: John Clements <john.clements@amd.com> Cc: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
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Luben Tuikov authored
Remove double-sscanf to scan for %llu and 0x%llx, as that is not going to work! The %llu will consume the "0" in "0x" of your input, and the hex value you think you're entering will always be 0. That is, a valid hex value can never be consumed. On the other hand, just entering a hex number without leading 0x will either be scanned as a string and not match, for instance FAB123, or the leading decimal portion is scanned as the %llu, for instance 123FAB will be scanned as 123, which is not correct. Thus remove the first %llu scan and leave only the %llx scan, removing the leading 0x since %llx can scan either. Addresses are usually always hex values, so this suffices. Cc: Alexander Deucher <Alexander.Deucher@amd.com> Cc: Xinhui Pan <xinhui.pan@amd.com> Cc: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
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Jinzhou Su authored
Add emit mem sync callback for sdma_v5_2 In amdgpu sync object test, three threads created jobs to send GFX IB and SDMA IB in sequence. After the first GFX thread joined, sometimes the third thread will reuse the same physical page to store the SDMA IB. There will be a risk that SDMA will read GFX IB in the previous physical page. So it's better to flush the cache before commit sdma IB. Signed-off-by:
Jinzhou Su <Jinzhou.Su@amd.com> Reviewed-by:
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Kent Russell authored
Like Arcturus, this isn't available on Aldebaran, so remove it accordingly Signed-off-by:
Kent Russell <kent.russell@amd.com> Reviewed-by:
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Anthony Koo authored
Signed-off-by:
Anthony Koo <Anthony.Koo@amd.com> Acked-by:
Bindu Ramamurthy <bindur12@amd.com> Tested-by:
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Aric Cyr authored
DC version 3.2.131 brings improvements in multiple areas. In summary, we highlight: -Enhancement for multiple eDP BL control. -Add debug flag to enable eDP ILR by default and debugfs to repress HPD/HPR_RX IRQ. -Fixes for DSC enable sequence,Force vsync flip,hang when psr is enabled etc. -Firmware releases: 0.0.60 0.0.61 Signed-off-by:
Aric Cyr <aric.cyr@amd.com> Acked-by:
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Roman Li authored
[Why] SKIP_CRTC_DISABLE bit should be applicable to all dcn asics not only Raven. [How] Replace check for Raven only with check for all DCNs. Signed-off-by:
Roman Li <Roman.Li@amd.com> Acked-by:
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