- 29 Nov, 2012 20 commits
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Daniel Vetter authored
To ditch at least some of the PCH_SPLIT ? PCH_LVDS : LVDS code ... v2: Rebase on top of Jani Nikula's panel rework. Reviewed-by:
Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by:
Daniel Vetter <daniel.vetter@ffwll.ch>
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Daniel Vetter authored
Yeah, all users (both the clock selection special cases and the lvds pin pair stuff) are still in common code, but this will change. v2: Rebase on top of Jani Nikula's panel rework. v3: Incorporate review from Paulo Zanoni: - s/__is_dual_link_lvds/compute_is_dual_link_lvds - kill dev_priv->lvds_val - drop spurious whitespace change v4: Add a debug printk to display the dual-link status, as suggested by Paulo Zanoni in review. Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> (v3) Signed-off-by: -
Daniel Vetter authored
Just a prep patch to make this a property of intel_lvds. Makes more sense, removes clutter from intel_display.c and eventually I want to move all the encoder special cases wrt clock handling to encoders anyway. v2: Add an intel_ prefixe to is_dual_link_lvds since it's non-static now. Reviewed-by:
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Daniel Vetter authored
... with is_dual_link_lvds introduced in commit b0354385 Author: Takashi Iwai <tiwai@suse.de> Date: Tue Mar 20 13:07:05 2012 +0100 drm/i915: Check VBIOS value for determining LVDS dual channel mode, too All these checks predate this commit and have simply been overlooked. Since we don't support switching between single-link and dual-link modes anyway, this different checks could at best only get in the way of refactorings, and in the worst case cause inconsistencies. v2: Update the comment, we now have a solid way to figure out whether we need dual-link lvds or not (falling back to vbt values as a last resort). We still don't know how to switch between dual-link and single link so leave that part intact. I'm not sure though whether switching between these two modes makes any sense - we always drive the panel at its fixed mode (with a fixed bpc) anyway ... Reviewed-by:
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Daniel Vetter authored
Currently we have two encoder specific bits in the common mode_set functions: - lvds pin pair enabling - dp m/n setting and computation Now the lvds stuff needs to happen before the pll is enabled. Since that is done in the crtc_mode_set functions, we need to add a new callback to be able to move them to the encoder code (where they belong). The dp m/n stuff is a giant mess anyway (since it also confuses itself with the fdi link m/n handling), so that needs to be handled separately. I think that we can move the pll enabling down quite a bit, which might allow us to eventually merge encoder->pre_enable with this new pre_pll_enable callback. But for now this will allow us to clean things up a bit. Note that vlv doesn't support lvds, hence we don't need to change anything in there. v2: Fixup commit message, both suggested from Paulo Zanoni. - dp m/n doesn't need to happen before pll enabling - lvds doesn't exist on vlv, hence no changes required in the vlv pll function. Reviewed-by:
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Chris Wilson authored
As we do not have any domains occupying the high bits, there is no point in always printing the leading 00. Signed-off-by:
Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by:
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Ville Syrjälä authored
As per Chris Wilson's suggestion make i915_gem_execbuffer_wait_for_flips() go away. This was used to stall the GPU ring while there are pending page flips involving the relevant BO. Ie. while the BO is still being scanned out by the display controller. The recommended alternative is to use the page flip events to wait for the page flips to fully complete before reusing the BO of the old front buffer. Or use more buffers. Signed-off-by:
Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by:
Kristian Høgsberg <krh@bitplanet.net> Acked-by:
Jesse Barnes <jbarnes@virtuousgeek.org> [danvet: don't remove obj->pending_flips, still required due to reorder patches.] Signed-off-by:
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Daniel Vetter authored
Somehow a chunk of unused register defines ended up in the middle of the PLL defines. They go back to the original kms merging. The only used #define is SR01, move it to the register name together with the other legacy vga stuff. Reviewed-by:
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Mika Kuoppala authored
i915_gem_handle_seqno_wrap() will zero all sync_seqnos but as the wrap can happen inside ring->sync_to(), pre wrap seqno was carried over and overwrote the zeroed sync_seqno. When wrap is handled, all outstanding requests will be retired and objects moved to inactive queue, causing their last_read_seqno to be zero. Use this to update the sync_seqno correctly. RING_SYNC registers after wrap will contain pre wrap values which are >= seqno. So injecting the semaphore wait into ring completes immediately. Original idea for using last_read_seqno from Chris Wilson. Signed-off-by:
Mika Kuoppala <mika.kuoppala@intel.com> Reviewed-by:
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Chris Wilson authored
Should be useful to know what the driver thought the other ring's seqno was when it last used a semaphore. Signed-off-by:
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Chris Wilson authored
Replace the wait for the ring to be clear with the more common wait for the ring to be idle. The principle advantage is one less exported intel_ring_wait function, and the removal of a hardcoded value. Signed-off-by:
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Chris Wilson authored
As we now always preallocate the seqno before writing to the ring, we can trivially test if we have any pending activity on the ring by inspecting the olr. This makes it then possible to flush operations that are not normally associated with a request, like power-management. Signed-off-by:
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Chris Wilson authored
Based on the work by Mika Kuoppala, we realised that we need to handle seqno wraparound prior to committing our changes to the ring. The most obvious point then is to grab the seqno inside intel_ring_begin(), and then to reuse that seqno for all ring operations until the next request. As intel_ring_begin() can fail, the callers must already be prepared to handle such failure and so we can safely add further checks. This patch looks like it should be split up into the interface changes and the tweaks to move seqno wrapping from the execbuffer into the core seqno increment. However, I found no easy way to break it into incremental steps without introducing further broken behaviour. v2: Mika found a silly mistake and a subtle error in the existing code; inside i915_gem_retire_requests() we were resetting the sync_seqno of the target ring based on the seqno from this ring - which are only related by the order of their allocation, not retirement. Hence we were applying the optimisation that the rings were synchronised too early, fortunately the only real casualty there is the handling of seqno wrapping. v3: Do not forget to reset the sync_seqno upon module reinitialisation, ala resume. Signed-off-by:
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Daniel Vetter authored
There seem to be indeed some awkwards machines around, mostly those without OpRegion support, where the firmware changes the display hw state behind our backs when closing the lid. This force-restore logic has been originally introduced in commit c1c7af60 Author: Jesse Barnes <jbarnes@virtuousgeek.org> Date: Thu Sep 10 15:28:03 2009 -0700 drm/i915: force mode set at lid open time but after the modeset-rework we've disabled it in the vain hope that it's no longer required: commit 3b7a89fc Author: Daniel Vetter <daniel.vetter@ffwll.ch> Date: Mon Sep 17 22:27:21 2012 +0200 drm/i915: fix OOPS in lid_notify Alas, no. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=54677 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=57434Tested-by:
Krzysztof Mazur <krzysiek@podlesie.net> Reviewed-by:
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Chris Wilson authored
In commit 69c2fc89 Author: Chris Wilson <chris@chris-wilson.co.uk> Date: Fri Jul 20 12:41:03 2012 +0100 drm/i915: Remove the per-ring write list the explicit flush was removed from i915_ring_idle(). However, we continued to wait upon the next seqno which now did not correspond to any request (except for the unusual condition of a failure to queue a request after execbuffer) and so would wait indefinitely. This has an important side-effect that i915_gpu_idle() does not cause the seqno to be incremented. This is vital if we are to be able to idle the GPU to handle seqno wraparound, as in subsequent patches. Signed-off-by:
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Mika Kuoppala authored
Dereference dev_priv only after we know it is valid. Found with smatch. Signed-off-by:
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Chris Wilson authored
Some devices may respond very slowly and only flag that the reply is pending within the first 15us response window. Be kind to such devices and wait a further 15ms, before checking for the pending reply. This moves the existing special case delay of 30ms down from the detection routine into the common path and pretends to explain it... v2: Simplify the loop constructs as suggested by Jani Nikula. References: https://bugs.freedesktop.org/show_bug.cgi?id=36997Signed-off-by:
Jani Nikula <jani.nikula@intel.com> Signed-off-by:
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Paulo Zanoni authored
We currently set "0" as the VIC value of the AVI InfoFrames. According to the specs this should be fine and work for every mode, so to my point of view we can't consider the current behavior as a bug. The problem is that we recently received a bug report (Kernel bug #50371) from a user that has an AV receiver that gives a black screen for any mode with VIC set to 0. So in order to make at least some modes work for him, this patch sets the correct VIC number when sending AVI InfoFrames. Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=50371Signed-off-by:
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Paulo Zanoni authored
This function returns the VIC of the mode. This value can be used when creating AVI InfoFrames. Cc: Thierry Reding <thierry.reding@avionic-design.de> Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=50371Signed-off-by:
Thierry Reding <thierry.reding@avionic-design.de> Acked-by:
Dave Airlie <airlied@gmail.com> Signed-off-by:
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Ben Widawsky authored
This bug was introduced by me: commit e76e9aeb Author: Ben Widawsky <ben@bwidawsk.net> Date: Sun Nov 4 09:21:27 2012 -0800 drm/i915: Stop using AGP layer for GEN6+ The existing code uses memset_io which follows memset semantics in only guaranteeing a write of individual bytes. Since a PTE entry is 4 bytes, this can only be correct if the scratch page address is 0. This caused unsightly errors when we clear the range at load time, though I'm not really sure what the heck is referencing that memory anyway. I caught this is because I believe we have some other bug where the display is doing reads of memory we feel should be cleared (or we are relying on scratch pages to be a specific value). Signed-off-by:
Ben Widawsky <ben@bwidawsk.net> Reviewed-by:
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- 23 Nov, 2012 1 commit
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Paulo Zanoni authored
Since it should be working a little bit better now. Signed-off-by:
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- 22 Nov, 2012 3 commits
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Chris Wilson authored
Signed-off-by:
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Chris Wilson authored
Use the recorded panel fixed-mode to populate the get_modes() request in the absence of an EDID. Fixes regression from commit 9cd300e0 Author: Jani Nikula <jani.nikula@intel.com> Date: Fri Oct 19 14:51:52 2012 +0300 drm/i915: Move cached EDID to intel_connector Signed-off-by:
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Jani Nikula authored
Since the base fields in both struct intel_connector and struct intel_sdvo_connector are at the beginning of the enclosing struct, the pointers are essentially the same, but there is no requirement or guarantee that this is always the case. Kfree the enclosing intel_sdvo_connector pointer that was originally allocated, not the enclosed drm_connector, in case someone ever rearranges the structs. Signed-off-by:
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- 21 Nov, 2012 16 commits
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Rob Clark authored
v2: Rebased. Signed-off-by:
Rob Clark <rob@ti.com> Reviewed-by: Jani Nikula <jani.nikula@intel.com> (v1) [danvet: Pimp commit message a bit.] Signed-off-by:
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Rob Clark authored
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Ben Widawsky authored
This was leftover crap from kill-agp. The current code is theoretically broken for 64b bars. (I resist removing theoretically because I am too lazy to test). We still need to ioremap things ourselves because we want to ioremap_wc the PTEs. v2: Forgot to kill the tmp variable in v1 CC: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by:
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Chris Wilson authored
If we have hit oom whilst holding our struct_mutex, then currently we cannot reap our own GPU buffers which likely pin most of memory, making an outright OOM more likely. So if we are running in direct reclaim and already hold the mutex, attempt to free buffers knowing that the original function can not continue until we return. v2: Add a note explaining that the mutex may be stolen due to pre-emption, and that is bad. Signed-off-by:
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Chris Wilson authored
As we may invoke the shrinker whilst trying to allocate memory to hold the gtt_space for this object, we need to be careful not to mark the drm_mm_node as activated (by assigning it to this object) before we have finished our sequence of allocations. Note: We also need to move the binding of the object into the actual pagetables down a bit. The best way seems to be to move it out into the callsites. Reported-by:
Imre Deak <imre.deak@gmail.com> Signed-off-by:
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Chris Wilson authored
As the SDVO/HDMI registers are multiplex, it is safe to assume that the w/a required for HDMI on IbexPoint, namely that the SDVO register cannot both be disabled and have selected transcoder B, is also required for SDVO. At least the modeset state checker detects that the transcoder selection is left in the undefined state, and so it appears sensible to apply the w/a: [ 1814.480052] WARNING: at drivers/gpu/drm/i915/intel_display.c:1487 assert_pch_hdmi_disabled+0xad/0xb5() [ 1814.480053] Hardware name: Libretto W100 [ 1814.480054] IBX PCH hdmi port still using transcoder B Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=57066Signed-off-by:
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Paulo Zanoni authored
Also document the WA name for the previous gens that implement it. Reviewed-by:
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Paulo Zanoni authored
For now, this code is just used by the eDP AUX channel frequency. Signed-off-by:
Damien Lespiau <damien.lespiau@intel.com> Signed-off-by:
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Paulo Zanoni authored
This goes on a separate patch since it won't apply on the stable trees and there's nothing using panel fitter on HSW on the older Kernels. Signed-off-by:
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Paulo Zanoni authored
I actually found this problem on Haswell, but then discovered Ivy Bridge also has it by reading the spec. I don't have the hardware to test this. Cc: stable@vger.kernel.org Signed-off-by:
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Paulo Zanoni authored
DDI A and E have 4 lanes to share, so if DDI A is using 4 lanes, there's nothing left for DDI E, which means there's no CRT port on the machine. The bit we're checking here is programmed at system boot and it cannot be changed afterwards, so we cannot change the amount of lanes reserved for each DDI port. Signed-off-by:
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Paulo Zanoni authored
We need to enable a special bit, otherwise none of the DP functions requiring the PCH will work. Version 2: store the PCH ID inside dev_priv, as suggested by Daniel Vetter. Signed-off-by:
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Paulo Zanoni authored
We don't check if the "unclaimed register" bit is set before we call writel, so if it was already set before, we might print a misleading message about "unclaimed write" on the wrong register. This patch makes us check the unclaimed bit before the writel, so we can print a new "Unknown unclaimed register before writing to %x" message. Signed-off-by:
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Paulo Zanoni authored
This function runs on Haswell, so set the correct pch_transcoder and cpu_transcoder variables. This fixes an assertion failure on Haswell VGA. Signed-off-by:
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Paulo Zanoni authored
This is a full revert of 59c859d6: drm/i915: account for only one PCH receiver on Haswell Now that the PCH code is fixed to be able use the only PCH transcoder independently of the pipe and CPU transcoder, we can revert this. Signed-off-by:
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Chris Wilson authored
If we accumulate unpin tasks because we are pageflipping faster than the system can schedule its workers, we can effectively create a pin-leak. The solution taken here is to limit the number of unpin tasks we have per-crtc and to flush those outstanding tasks if we accumulate too many. This should prevent any jitter in the normal case, and also prevent the hang if we should run too fast. Note: It is important that we switch from the system workqueue to our own dev_priv->wq since all work items on that queue are guaranteed to only need the dev->struct_mutex and not any modeset resources. For otherwise if we have a work item ahead in the queue which needs the modeset lock (like the output detect work used by both polling or hpd), this work and so the unpin work will never execute since the pageflip code already holds that lock. Unfortunately there's no lockdep support for this scenario in the workqueue code. Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=46991Reported-and-tested-by:
Tvrtko Ursulin <tvrtko.ursulin@onelan.co.uk> Signed-off-by:
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