- 07 Jan, 2014 40 commits
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Hans Verkuil authored
Add a proper driver strength enum and use the same names in the platform data as with adv7604. Signed-off-by:
Hans Verkuil <hans.verkuil@cisco.com> Signed-off-by:
Mauro Carvalho Chehab <m.chehab@samsung.com>
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Hans Verkuil authored
This timing must be supported by all HDMI equipment, so that's a reasonable default. Signed-off-by:
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Hans Verkuil authored
The correct LLC DLL phase depends on the board layout, so this should be part of the platform_data. Also updated the platform_data in ezkit to ensure that what was the old default value is now explicitly specified, so the behavior for that board is unchanged. Tested-by:
Martin Bugge <marbugge@cisco.com> Signed-off-by:
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Martin Bugge authored
Return 0 if the new timings are equal to the current timings as it caused extra cp-loss/lock interrupts. Signed-off-by:
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Martin Bugge authored
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Martin Bugge authored
The free-run mode can be board-specific. Also updated the platform_data in ezkit to ensure that what was the old default value is now explicitly specified, so the behavior for that board is unchanged. Signed-off-by:
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Martin Bugge authored
Must clear timings before setting after test to recover. Signed-off-by:
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Martin Bugge authored
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Martin Bugge authored
Clear i2c_clients ptr when unregistered. Warn if configured i2c-addr is zero. Signed-off-by:
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Martin Bugge authored
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Martin Bugge authored
The STDI block may measure wrong values, especially for lcvs and lcf. If the driver can not find any valid timing, the STDI block is restarted to measure the video timings again. The function will return an error, but the restart of STDI will generate a new STDI interrupt and the format detection process will restart. Copied from adv7604. Signed-off-by:
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Martin Bugge authored
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Mats Randgaard authored
Signed-off-by:
Mats Randgaard <matrandg@cisco.com> Signed-off-by:
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Mats Randgaard authored
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Mats Randgaard authored
May also be wrong if the receiver is connected to more than one connector. Signed-off-by:
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Martin Bugge authored
Wait 5ms after main reset. The data-sheet doesn't specify the wait after i2c-controlled reset, so using same value as after pin-controlled reset. Signed-off-by:
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Martin Bugge authored
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Martin Bugge authored
Both the PAL and NTSC standards are interlaced where a frame consist of two fields. Total number of lines in a frame in both systems are an odd number so the two fields will have different length. In the 625 line standard ("PAL") the odd field of the frame is transmitted first, while in the 525 standard ("NTSC") the even field is transmitted first. This adds the possibility to change output config between the fields and standards. This setting will reduce the "format-jitter" on the signal sent by the pixelport moving the difference between the fields to vertical front/back-porch only. Signed-off-by: -
Martin Bugge authored
For edid with no Source Physical Address (spa), set spa-location to default and use correct values from edid. Signed-off-by:
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Hans Verkuil authored
Added support for YCrCb analog input. If input is ADV7842_MODE_RGB and RGB quantization range is set to V4L2_DV_RGB_RANGE_AUTO, then video with CEA timings will be received as RGB. For ADV7842_MODE_COMP, automatic CSC mode will be selected. See table 48 on page 281 in "ADV7842 Hardware Manual, Rev. 0, January 2011" for details. Make sure that when switching inputs the RGB quantization range is updated as well. Also updated the platform_data in ezkit to ensure that what was the old default value is now explicitly specified, so the behavior for that board is unchanged. Signed-off-by:
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Martin Bugge authored
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Martin Bugge authored
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Martin Bugge authored
The method of disabling the irq-output pin caused many "empty" interrupts. Instead, actually disable/enable the interrupts by changing the interrupt masks. Also enable STORE_MASKED_IRQ in INT1 configuration, otherwise when HDMI events happen while the interrupt is masked those events will be ignored when the interrupt is unmasked. Signed-off-by:
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Martin Bugge authored
Bit 6 of register 0x8f was cleared incorrectly (must be 1), and bit 4 of register 0x91 was set incorrectly (must be 0). These bits are undocumented, so we shouldn't modify them to values different from what the datasheet specifies. Signed-off-by:
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Martin Bugge authored
This simplified the code quite a bit. Signed-off-by:
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Hans Verkuil authored
This timing must be supported by all HDMI equipment, so that's a reasonable default. Signed-off-by:
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Martin Bugge authored
Signed-off-by:
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Mats Randgaard authored
Signed-off-by:
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Mats Randgaard authored
Some sources are initially detected as DVI, and change to HDMI later. This must be detected to set the right RGB quantization range. Signed-off-by:
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Mats Randgaard authored
If the input signal is DVI-D and quantization range is RGB full range, gain and offset must be adjusted to get the right range on the output. Signed-off-by:
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Martin Bugge authored
If the restart_stdi_once trick fails to find a valid format the flag was never reset. Signed-off-by:
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Mats Randgaard authored
- Mute audio before switching inputs to avoid noise/pops - Mute audio if audio FIFO over-/underflows (AD Recommended setting) - Reset FIFO if it over-/underflows (AD Recommended setting) Signed-off-by:
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Mats Randgaard authored
ADV7604_FMT_CHANGE events was debounced in adv7604_isr() to avoid that a receiver with a unstable input signal would block the event handling for other inputs. This solution was prone to errors. A better protection agains interrupt blocking is to delay the call of the interrupt service routine in the adv7604 driver if too many interrupts are received within a given time. Signed-off-by:
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Mats Randgaard authored
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Mats Randgaard authored
May also be wrong if the receiver is connected to more than one connector. Signed-off-by:
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Mats Randgaard authored
- split edid_write_block() - do not use edid->edid before the validity check - Return -EINVAL if edid->pad is invalid - Save both registers for SPA port A - Set SPA location to default value if it is not found Signed-off-by:
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Mats Randgaard authored
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Mats Randgaard authored
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Mats Randgaard authored
If the input is ADV7604_INPUT_VGA_RGB and RGB quantization range is set to V4L2_DV_RGB_RANGE_AUTO, video with CEA timings will be received as RGB. For ADV7604_INPUT_VGA_COMP, automatic CSC mode will be selected. See table 44 on page 205 in "ADV7604 Hardware Manual, Rev. F, August 2010" for details. Signed-off-by:
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Hans Verkuil authored
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