- 25 Jul, 2023 36 commits
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Pierre-Eric Pelloux-Prayer authored
This allows tools to distinguish between VRAM and visible VRAM. Use the opportunity to fix locking before accessing bo. v2: squash in unused variable fix Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Alex Sierra authored
Set dynamic_svm_range_dump macro to avoid iterating over SVM lists from svm_range_debug_dump when dynamic debug is disabled. Otherwise, it could drop performance, specially with big number of SVM ranges. Make sure both svm_range_set_attr and svm_range_debug_dump functions are dynamically enabled to print svm_range_debug_dump debug traces. Signed-off-by:
Alex Sierra <alex.sierra@amd.com> Tested-by:
Philip Yang <Philip.Yang@amd.com> Reviewed-by:
Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by:
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Ran Sun authored
Fix two occurrences of the checkpatch.pl error: ERROR: "foo * bar" should be "foo *bar" Signed-off-by:
Ran Sun <sunran001@208suo.com> Signed-off-by:
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Ran Sun authored
ERROR: open brace '{' following struct go on the same line Signed-off-by: -
Ran Sun authored
ERROR: open brace '{' following struct go on the same line Signed-off-by: -
Ran Sun authored
Fix the checkpatch error as open brace '{' following struct should go on the same line. Signed-off-by: -
Dan Carpenter authored
This error path needs to unlock the "aconnector->handle_mst_msg_ready" mutex before returning. Fixes: bb4fa525 ("drm/amd/display: Add polling method to handle MST reply packet") Signed-off-by:
Dan Carpenter <dan.carpenter@linaro.org> Signed-off-by:
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Aric Cyr authored
This version brings along following fixes: - Fix underflow issue on 175hz timing - Add interface to modify DMUB panel power options - Remove check for default eDP panel_mode - Add new sequence for 4-lane HBR3 on vendor specific retimers - Update DPG test pattern programming - Correct unit conversion for vstartup - Exit idle optimizations before attempt to access PHY - Refactor recout calculation with a more generic formula - Read down-spread percentage from lut to adjust dprefclk. - Don't apply FIFO resync W/A if rdivider = 0 - Prevent invalid pipe connections - Rearrange dmub_cmd defs order - Add VESA SCR case for default aux backlight - Guard DCN31 PHYD32CLK logic against chip family - Correct grammar mistakes Acked-by:
Alex Hung <alex.hung@amd.com> Signed-off-by:
Aric Cyr <aric.cyr@amd.com> Tested-by:
Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by:
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Leo Ma authored
[Why] Screen underflows happen on 175hz timing for 3 plane overlay case. [How] Based on dst y prefetch value clamp to equ or oto for bandwidth calculation. Reviewed-by:
Dillon Varone <dillon.varone@amd.com> Acked-by:
Leo Ma <hanghong.ma@amd.com> Tested-by:
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Paul Hsieh authored
[Why] This option can vary depending on the panel and may be required to be called during sink detection phase before transmitter control. [How] Allow modify the bit depending on the eDP panel connected with a new interface. Reviewed-by:
Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Acked-by:
Paul Hsieh <paul.hsieh@amd.com> Tested-by:
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Anthony Koo authored
- Rearranged defs order Acked-by:
Anthony Koo <anthony.koo@amd.com> Tested-by:
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Taimur Hassan authored
[Why] DPCD read is skipped first time after driver initialization. Reviewed-by:
Charlene Liu <charlene.liu@amd.com> Acked-by:
Taimur Hassan <syed.hassan@amd.com> Tested-by:
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Srinivasan Shanmugam authored
Fixes the following to align to linux coding style: WARNING: braces {} are not necessary for any arm of this statement WARNING: Missing a blank line after declarations ERROR: space prohibited before that close parenthesis ')' WARNING: unnecessary whitespace before a quoted newline WARNING: %LX is non-standard C, use %llX Cc: Christian König <christian.koenig@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Signed-off-by:Srinivasan Shanmugam <srinivasan.shanmugam@amd.com> Reviewed-by:
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Ovidiu Bunea authored
[Why] In some vendor specific retimer setups for downstream 4-lane HBR3 configuration, the sink will show severe corruption (horizontal shifting) and intermittent blanking. [How] Add new retimer programming sequence before clock recovery when 4 lanes are active. Reviewed-by:
Michael Strauss <michael.strauss@amd.com> Acked-by:
Ovidiu Bunea <ovidiu.bunea@amd.com> Tested-by:
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Wenjing Liu authored
[Why] Last ODM slice could be slightly larger than other slice because it can be including the residual. [How] Update DPG pattern programming sequence to use a different width for last odm slice. Reviewed-by:
Chris Park <chris.park@amd.com> Acked-by:
Wenjing Liu <wenjing.liu@amd.com> Tested-by:
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Reza Amini authored
[Why] vstartup is calculated to be a large number. It works because it is within vertical blank, but it reduces region of blank that can be used for power gating. [How] Calculation needs to convert micro seconds to number of vertical lines. Reviewed-by:
Reza Amini <reza.amini@amd.com> Tested-by:
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Leo Chen authored
[Why & How] DMUB may hang when powering down pixel clocks due to no dprefclk. It is fixed by exiting idle optimization before the attempt to access PHY. Reviewed-by:
Leo Chen <sancchen@amd.com> Tested-by:
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Wenjing Liu authored
[Why] Current recout calculation has a few assumptions and implementation for MPO + ODM combine calculation is very specific. The equation has too many cases without enough comments to document the detail. [How] The change remove the following assumptions: 1. When MPO is enabled, we only allow ODM Combine 2:1 2. ODM Combine always has even segment width. 3. Secondary MPO plane's pipe_ctx copies pre_odm_pipe from its top pipe. The change applies a generic formula with more details in comment to document this solution so it is eaiser to learn and debug later. Reviewed-by:
Dmytro Laktyushkin <dmytro.laktyushkin@amd.com> Acked-by:
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Martin Tsai authored
[Why] Panels show corruption with high refresh rate timings when ss is enabled. [How] Read down-spread percentage from lut to adjust dprefclk. Reviewed-by:
Martin Tsai <martin.tsai@amd.com> Tested-by:
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Alvin Lee authored
[Description] It is not valid to set the WDIVIDER value to 0, so do not re-write to DISPCLK_WDIVIDER if the current value is 0 (i.e., it is at it's initial value and we have not made any requests to change DISPCLK yet). Reviewed-by:
Saaem Rizvi <syedsaaem.rizvi@amd.com> Acked-by:
Alvin Lee <alvin.lee2@amd.com> Tested-by:
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Ethan Bitnun authored
[Description] - Prevent ODM pipe connections between pipes that are not part of the same plane when adding a plane to context - Re-attach child pipes of ODM slice about to be disconnected to prevent any lost pipes with invalid tops/bottoms - We cannot split if head_pipe is not in ODM. Preventing this avoids creating an invalid context with an invalid pipe. Reviewed-by:
Ethan Bitnun <ethan.bitnun@amd.com> Tested-by:
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Lijo Lazar authored
Not all rings have scheduler associated. Only update scheduler data for rings with scheduler. It could result in out of bound access as total rings are more than those associated with particular IPs. Signed-off-by:
Lijo Lazar <lijo.lazar@amd.com> Reviewed-by:
James Zhu <James.Zhu@amd.com> Signed-off-by:
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sguttula authored
This patch will enable VCN FW workaround using DRM KEY INJECT WORKAROUND method, which is helping in fixing the secure playback. Signed-off-by:
sguttula <Suresh.Guttula@amd.com> Reviewed-by:
Leo Liu <leo.liiu@amd.com> Signed-off-by:
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Iswara Nagulendran authored
[How & Why] When determining default aux backlight level, read from DPCD address 0x734 for VESA SCR on OLED. Reviewed-by:
Felipe Clark <felipe.clark@amd.com> Acked-by:
Iswara Nagulendran <iswara.nagulendran@amd.com> Tested-by:
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Srinivasan Shanmugam authored
Changed from pr_err/info to dev_* variants so that we get better debug info when there are multiple GPUs in the system. Fixes: 09edeb4c ("drm/radeon: Prefer pr_err/_info over printk") Suggested-by:
Evan Quan <evan.quan@amd.com> Signed-off-by:
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Srinivasan Shanmugam authored
Conform to Linux kernel coding style. Fixes the following & other checks in radeon_encoders.c & radeon_gart.c: WARNING: Missing a blank line after declarations WARNING: Block comments use * on subsequent lines WARNING: Prefer 'unsigned int' to bare use of 'unsigned' WARNING: braces {} are not necessary for single statement blocks Cc: Christian König <christian.koenig@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Signed-off-by:Guchun Chen <guchun.chen@amd.com> Signed-off-by:
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Srinivasan Shanmugam authored
Fixes the below checkpatch.pl warnings: WARNING: Block comments use * on subsequent lines WARNING: Block comments use a trailing */ on a separate line WARNING: suspect code indent for conditional statements (8, 12) WARNING: braces {} are not necessary for single statement blocks Cc: Christian König <christian.koenig@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: -
Srinivasan Shanmugam authored
Fixes the following: - WARNING: externs should be avoided in .c files - ERROR: do not initialise globals to 0 - WARNING: Missing a blank line after declarations Cc: Christian König <christian.koenig@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Signed-off-by:
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George Shen authored
[Why] Current yellow carp B0 PHYD32CLK logic is incorrectly applied to other ASICs. [How] Add guard to check chip family is yellow carp before applying logic. Reviewed-by:
Hansen Dsouza <hansen.dsouza@amd.com> Acked-by:
George Shen <george.shen@amd.com> Tested-by:
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Reza Amini authored
[Why] There are grammer mistakes in comments [How] Correct grammar mistakes Reviewed-by:
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Srinivasan Shanmugam authored
Return -ENOMEM, when there is no sufficient dynamically allocated memory to create MQD backup for ring Cc: Christian König <christian.koenig@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Signed-off-by:
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Srinivasan Shanmugam authored
Fixes the following to align to coding style: WARNING: do not add new typedefs +typedef struct FW_ATT_DB_HEADER WARNING: do not add new typedefs +typedef struct FW_ATT_RECORD WARNING: Symbolic permissions 'S_IRUSR' are not preferred. Consider using octal permissions '0400'. + S_IRUSR, ERROR: "(foo*)" should be "(foo *)" WARNING: please, no space before tabs Cc: Christian König <christian.koenig@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Signed-off-by:
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Srinivasan Shanmugam authored
Adhere to linux coding style Fixes the following: WARNING: Prefer IS_ENABLED(<FOO>) to CONFIG_<FOO> || CONFIG_<FOO>_MODULE +#if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE) WARNING: Prefer IS_ENABLED(<FOO>) to CONFIG_<FOO> || CONFIG_<FOO>_MODULE +#if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE) Cc: Christian König <christian.koenig@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Signed-off-by:
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Jonathan Kim authored
MES can concurrently schedule queues on the device that require exclusive device access if marked exclusively_scheduled without the requirement of GWS. Similar to the F32 HWS, MES will manage quality of service for these queues. Use this for cooperative groups since cooperative groups are device occupancy limited. Since some GFX11 devices can only be debugged with partial CUs, do not allow the debugging of cooperative groups on these devices as the CU occupancy limit will change on attach. In addition, zero initialize the MES add queue submission vector for MES initialization tests as we do not want these to be cooperative dispatches. Signed-off-by:
Jonathan Kim <jonathan.kim@amd.com> Reviewed-by:
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Horace Chen authored
[Why] Current SR-IOV will not set GC to off state, while it is a real GC hard reset. Whthout GFX off flag, driver may do gfxhub invalidation before firmware load and gfxhub gart enable. This operation may cause CP to become busy because GC is not in the right state for invalidation. [How] Add a function for SR-IOV to clean up some sw state before recover. Set adev->gfx.is_poweron to false to prevent gfxhub invalidation before gfx firmware autoload complete. Signed-off-by:
Horace Chen <horace.chen@amd.com> Reviewed-by:
HaiJun Chang <HaiJun.Chang@amd.com> Signed-off-by:
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Jane Jian authored
Report current GFX clock also from average clock value as the original CurrClock data is not valid/accurate any more as per FW team Signed-off-by:
Jane Jian <Jane.Jian@amd.com> Reviewed-by:
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- 21 Jul, 2023 4 commits
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Yang Li authored
Use colon to separate parameter name from their specific meaning. silence the warning: drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c:793: warning: Function parameter or member 'adev' not described in 'amdgpu_vm_pte_update_noretry_flags' Reviewed-by:
Randy Dunlap <rdunlap@infradead.org> Signed-off-by:
Yang Li <yang.lee@linux.alibaba.com> Signed-off-by:
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Mario Limonciello authored
If the second call to amdgpu_bo_create_kernel() fails, the memory allocated from the first call should be cleared. If the third call fails, the memory from the second call should be cleared. Fixes: b95b5391 ("drm/amdgpu/psp: move PSP memory alloc from hw_init to sw_init") Signed-off-by:
Mario Limonciello <mario.limonciello@amd.com> Reviewed-by:
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Victor Lu authored
An instance of for_each_inst() was not changed to match its new behaviour and is causing a loop. v2: remove tmp_mask variable Fixes: b579ea63 ("drm/amdgpu: Modify for_each_inst macro") Signed-off-by:
Victor Lu <victorchengchi.lu@amd.com> Acked-by:
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Lijo Lazar authored
XCP_CTL register is expected to be programmed by firmware. Under certain conditions FW may not have programmed it correctly. As a workaround, program it when FW has not programmed the right values. Signed-off-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
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