- 16 Jun, 2017 4 commits
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Hanna Hawa authored
This commit adds a pinctrl driver for the pin-muxing controller found in the AP806 part of the Marvell Armada 7K and 8K SoCs. Its register interface is compatible with the one used by previous mvebu pin controllers, so the common logic in drivers/pinctrl/mvebu/pinctrl-mvebu.c is used. Signed-off-by:
Hanna Hawa <hannah@marvell.com> Reviewed-by:
Shadi Ammouri <shadi@marvell.com> [updated for mvebu pinctrl changes - converted to simple_mmio - removed unimplemented .remove function - removed DTS description - converted to use syscon/regmap --rmk] Signed-off-by:
Russell King <rmk+kernel@armlinux.org.uk> Reviewed-by:
Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by:
Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by:
Linus Walleij <linus.walleij@linaro.org>
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Russell King authored
Armada 8040 also needs orion pinctrl, and as these symbols are only selected, there's no need to make them depend on PLAT_ORION. Reviewed-by:
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Gregory CLEMENT authored
The offset property of the pinctrl node, when a regmap is used in the device tree, was never used nor documented in the binding. Moreover, the compatible string is enough to let the driver know which offset using. So this patch removes the property and move the information at the driver level. Reviewed-by:
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Jerome Brunet authored
Add Tsin A pins to bank DV and X. We don't have a driver for the tsin yet but since the tsin A pinmux is enabled by default at boot time, declaring this pinmux is required to properly operate on GPIOX. Without this change, GPIOX 8, 9, 10 and 11 can't be driven as GPIO output as the tsin A seems to have priority. Signed-off-by:
Jerome Brunet <jbrunet@baylibre.com> Acked-by:
Neil Armstrong <narmstrong@baylibre.com> Signed-off-by:
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- 09 Jun, 2017 10 commits
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Mika Westerberg authored
This adds pinctrl/GPIO support for Intel Cannon Lake PCH. The Cannon Lake PCH GPIO is based on newer version of the Intel GPIO hardware. Signed-off-by:
Mika Westerberg <mika.westerberg@linux.intel.com> Reviewed-by:
Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by:
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Mika Westerberg authored
On some SoCs not all pins in a group use the same mode when a certain function is muxed out of them. This makes it possible to specify mode per pin as an array instead in addition to single integer. Signed-off-by:
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Mika Westerberg authored
The Intel GPIO hardware has a concept of pad groups, which means 1 to 32 pads occupying their own GPI_IS, GPI_IE, PAD_OWN and so on registers. The existing hardware has the same amount of pads in each pad group (except the last one) so it is possible to use community->gpp_size to calculate start offset of each register. With the next generation SoCs the pad group size is not always the same anymore which means we cannot use community->gpp_size for register offset calculations directly. To support variable size pad groups we introduce struct intel_padgroup that can be filled in by the client drivers according the hardware pad group layout. The core driver will always use these when it performs calculations for pad register offsets. The core driver will automatically populate pad groups based on community->gpp_size if the driver does not provide any. This makes sure the existing drivers still work as expected. Signed-off-by:
Chuah, Kim Tatt <kim.tatt.chuah@intel.com> Signed-off-by:
Tan Jui Nee <jui.nee.tan@intel.com> Reviewed-by:
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Chen-Yu Tsai authored
The R_PIO on the A83T is almost the same as the one found on the A64, except that the CIR_RX function was moved from pin PL11 to pin PL12. Add a driver for it. Signed-off-by:
Chen-Yu Tsai <wens@csie.org> Acked-by:
Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by:
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Chen-Yu Tsai authored
The R_PIO on the A83T is almost the same as the one found on the A64, except that the CIR_RX function was moved from pin PL11 to pin PL12. Add a compatible string for it. Signed-off-by:
Rob Herring <robh@kernel.org> Acked-by:
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Scott Branden authored
Use consistent license headers for Broadcom files by placing additional comments outside of standard legal header. Also, update legal header to 2017 format as "Broadcom Corporation" has changed to "Broadcom". Signed-off-by:
Scott Branden <scott.branden@broadcom.com> Reviewed-by:
Florian Fainelli <f.fainelli@gmail.com> Signed-off-by:
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Tobias Klauser authored
struct irq_domain_ops is not modified, so it can be made const. Suggested-by:
Marc Zyngier <marc.zyngier@arm.com> Signed-off-by:
Tobias Klauser <tklauser@distanz.ch> Acked-by:
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Alexandre TORGUE authored
There is no link between the number of elements of tab which contains all pin desc (located in each pinctrl-stm32xxxx.c files) and the pin number (defined in the tab). Signed-off-by:
Alexandre TORGUE <alexandre.torgue@st.com> Signed-off-by:
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Jerome Brunet authored
Add GPIO interrupt information to pinctrl data. Added to the original version from Jerome was data for Meson GXL. Signed-off-by:
Heiner Kallweit <hkallweit1@gmail.com> Acked-by:
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Heiner Kallweit authored
After commit 34e61801 "pinctrl: meson-gxbb: Add missing GPIODV_18 pin entry" I started to get the following warning: "meson-pinctrl c8834000.periphs:pinctrl@4b0: names 119 do not match number of GPIOs 120" It turned out that not the mentioned commit has a problem, it just revealed another problem which had existed before. There is no PIN GPIOX_22 on Meson GXBB. Fixes: 468c234f ("pinctrl: amlogic: Add support for Amlogic Meson GXBB SoC") Signed-off-by:
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- 31 May, 2017 3 commits
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Linus Walleij authored
Merge tag 'sh-pfc-for-v4.13-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel pinctrl: sh-pfc: Updates for v4.13 - Add PWM, AVB MDIO/MII, and sound pin groups on R-Car M3-W, - Add support for RZ/G1M and RZ/G1E, - Small fixes and cleanups.
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Alexandre TORGUE authored
Add .get_direction() gpiochip callback in STM32 pinctrl driver. Signed-off-by:
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Alexandre TORGUE authored
This patch ensures that pin is correctly set as gpio input when it is used as an interrupt. Signed-off-by:
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- 30 May, 2017 1 commit
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Arnd Bergmann authored
With "SPI_MASTER=y && I2C=m", we can build mcp23s08 as a built-in driver, which then results in a link failure: drivers/pinctrl/built-in.o: In function `mcp23s08_probe_one.isra.0': :(.text+0x7910): undefined reference to `__devm_regmap_init_i2c' drivers/pinctrl/built-in.o: In function `mcp23s08_init': :(.init.text+0x110): undefined reference to `i2c_register_driver' drivers/pinctrl/built-in.o: In function `mcp23s08_exit': :(.exit.text+0x3c): undefined reference to `i2c_del_driver' To avoid the problem, this adds another dependency on I2C that enforces mcp23s08 to be a loadable module whenever the I2C core is a module. Fixes: 64ac43e6 ("gpio: mcp23s08: move to pinctrl") Signed-off-by:
Arnd Bergmann <arnd@arndb.de> Reviewed-by:
Sebastian Reichel <sebastian.reichel@collabora.co.uk> Signed-off-by:
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- 29 May, 2017 22 commits
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Martin Schiller authored
Signed-off-by:
Martin Schiller <ms@dev.tdt.de> Signed-off-by:
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Icenowy Zheng authored
Allwinner R40 has a pin controller like the ones in older Allwinner SoCs (especially A20), and can use modified version of the A10/A20 pinctrl driver. Add a compatible string for it. Signed-off-by:
Icenowy Zheng <icenowy@aosc.io> Acked-by:
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Icenowy Zheng authored
As we added A20 support to A10 pinctrl driver, now we can delete the dedicated A20 pinctrl driver, which is duplicated code. Signed-off-by:
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Icenowy Zheng authored
As A20 is designed as a pin-compatible upgrade of A10, their pin controller are very similar, and can share one driver. Add A20 support to the A10 driver. Signed-off-by:
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Icenowy Zheng authored
Allwinner A10, A20 and R40 SoCs have similar GPIO layout. Add SoC definitions in pinctrl-sunxi.h, in order to merge A20 support into A10 driver, and add R40 support into it. Signed-off-by:
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David Wu authored
There are 2 IP blocks pin routes need to be switched, that are uart2dbg, pcie_clkreq. Signed-off-by:
David Wu <david.wu@rock-chips.com> Reviewed-by:
Heiko Stuebner <heiko@sntech.de> Signed-off-by:
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David Wu authored
There are 8 IP blocks pin routes need to be switched, that are uart2dbg, gmac-m1-optimized, pdm, spi, i2s2, card, tsp, cif. Signed-off-by:
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David Wu authored
There are 9 IP blocks pin routes need to be switched, that are pwm-0, pwm-1, pwm-2, pwm-3, sdio, spi, emmc, uart2, uart1. Signed-off-by:
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David Wu authored
On the some rockchip SOCS, some things like rk3399 specific uart2 can use multiple pins. Somewhere between the pin io-cells and the uart it seems to have some sort of switch to decide to which pin to actually route the data. +-------+ +--------+ /- GPIO4_B0 (pinmux 2) | uart2 | -- | switch | --- GPIO4_C0 (pinmux 2) +-------+ +--------+ \- GPIO4_C3 (pinmux 2) (switch selects one of the 3 pins base on the GRF_SOC_CON7[BIT0, BIT1]) The routing switch is determined by one pin of a specific group to be set to its special pinmux function. If the pinmux setting is wrong for that pin the ip block won't work correctly anyway. Signed-off-by:
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Linus Walleij authored
Fix compile errors due to missing OF. Cc: Paul Cercueil <paul@crapouillou.net> Reported-by:
Randy Dunlap <rdunlap@infradead.org> Signed-off-by:
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Neil Armstrong authored
The Amlogic Meson GXL SoCs embeds an 10/100 Ethernet PHY, this patchs enables the Link and Activity LEDs signals. Signed-off-by:
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Neil Armstrong authored
Add the AO and EE domain CEC pins for the Amlogic Meson GXL SoCs. Signed-off-by:
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Neil Armstrong authored
Add the AO and EE domain CEC pins for the Amlogic Meson GXBB SoCs. Signed-off-by:
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Neil Armstrong authored
The AO SPDIF pins were incorrectly defined with the EE pin offset. Fixes: b840d649 ("pinctrl: meson: gxl: add spdif output pins") Signed-off-by:
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Neil Armstrong authored
The AO I2S pins were incorrectly defined with the EE pin offset. Fixes: 2899adf0 ("pinctrl: meson: gxl: add i2s output pins") Signed-off-by:
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Neil Armstrong authored
GPIODV_18 entry was missing in the original driver push. Fixes: 468c234f ("pinctrl: amlogic: Add support for Amlogic Meson GXBB SoC") Signed-off-by:
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Neil Armstrong authored
GPIODV_18 entry was missing in the original driver push. Fixes: 0f15f500 ("pinctrl: meson: Add GXL pinctrl definitions") Signed-off-by:
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Paul Gortmaker authored
Fixups here tend to be more of a conglomerate of some of the other repeated/systematic ones we've seen in the earlier pinctrl cleanups. We remove module.h from code that isn't doing anything modular at all; if they have __init sections, then replace it with init.h One driver has a .remove that would be dispatched on module_exit, and as that code is essentially orphaned, so we remove it. In case anyone was previously doing the (pointless) unbind to get to that function, we disable unbind for this one driver as well. A couple bool drivers (hence non-modular) are converted over to to builtin_platform_driver(). Since module_platform_driver() uses the same init level priority as builtin_platform_driver() the init ordering remains unchanged with this commit. Also note that MODULE_DEVICE_TABLE is a no-op for non-modular code. We also delete the MODULE_LICENSE tag etc. since all that information was (or is now) contained at the top of the file in the comments. Cc: Eric Anholt <eric@anholt.net> Cc: Florian Fainelli <f.fainelli@gmail.com> Cc: Jon Mason <jonmason@broadcom.com> Cc: Linus Walleij <linus.walleij@linaro.org> Cc: Ray Jui <rjui@broadcom.com> Cc: Scott Branden <sbranden@broadcom.com> Cc: Sherman Yin <syin@broadcom.com> Cc: bcm-kernel-feedback-list@broadcom.com Cc: linux-gpio@vger.kernel.org Cc: linux-rpi-kernel@lists.infradead.org Signed-off-by:
Paul Gortmaker <paul.gortmaker@windriver.com> Tested-by:
Stefan Wahren <stefan.wahren@i2se.com> Signed-off-by:
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Paul Gortmaker authored
None of the Kconfigs for any of these drivers are tristate, meaning that they currently are not being built as a module by anyone. Lets remove the modular code that is essentially orphaned, so that when reading the drivers there is no doubt they are builtin-only. All drivers get similar changes, so they are handled in batch. We remove module.h from code that isn't doing anything modular at all; if they have __init sections, then replace it with init.h. A couple drivers have module_exit() code that is essentially orphaned, and so we remove that. Quite a few bool drivers (hence non-modular) are converted over to to builtin_platform_driver(). Since module_platform_driver() uses the same init level priority as builtin_platform_driver() the init ordering remains unchanged with this commit. Also note that MODULE_DEVICE_TABLE is a no-op for non-modular code. We also delete the MODULE_LICENSE tag etc. since all that information was (or is now) contained at the top of the file in the comments. Cc: Linus Walleij <linus.walleij@linaro.org> Cc: Stephen Warren <swarren@wwwdotorg.org> Cc: Thierry Reding <thierry.reding@gmail.com> Cc: Alexandre Courbot <gnurou@gmail.com> Cc: Pritesh Raithatha <praithatha@nvidia.com> Cc: Ashwini Ghuge <aghuge@nvidia.com> Cc: linux-gpio@vger.kernel.org Cc: linux-tegra@vger.kernel.org Signed-off-by:
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Masahiro Yamada authored
Use of_device_get_match_data() instead of of_match_device(). It allows us to remove the forward declaration of pcs_of_match. Signed-off-by:
Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by:
Tony Lindgren <tony@atomide.com> Signed-off-by:
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Shawn Guo authored
There are a couple of issues with group_desc initialization in function zx_pinctrl_build_state(). - num_pins is not initialized and remains zero. - pins shouldn't be initialized with a pointer to variable in the stack. With them fixed, pin_request() in pinmux_enable_setting() can be invoked correctly. Signed-off-by:
Shawn Guo <shawn.guo@linaro.org> Signed-off-by:
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Neil Armstrong authored
The SPICC controller has dedicated SPI pins, this patchs add the pins definition in the GXBB pinctrl driver Signed-off-by:
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