- 08 May, 2024 40 commits
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Tim Huang authored
Clear warning that read ucode[] may out-of-bounds. Signed-off-by:
Tim Huang <Tim.Huang@amd.com> Reviewed-by:
Alex Deucher <alexander.deucher@amd.com> Signed-off-by:
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Ma Jun authored
Function .set_power_profile_mode need an array as input parameter. So define variable workload as an array to fix the below coverity warning. "Passing &workload to function hwmgr->hwmgr_func->set_power_profile_mode which uses it as an array. This might corrupt or misinterpret adjacent memory locations" Signed-off-by:
Ma Jun <Jun.Ma2@amd.com> Acked-by:
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Ma Jun authored
Check the return value of amdgpu_xcp_get_inst_details, otherwise we may use an uninitialized variable inst_mask Signed-off-by:
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Ma Jun authored
Check the fb_channel_number range to avoid the array out-of-bounds read error Signed-off-by:
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Alex Deucher authored
This fixes HDP flushes on systems with non-4K pages. Reviewed-by:
Felix Kuehling <felix.kuehling@amd.com> Signed-off-by:
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Alex Deucher authored
This fixes HDP flushes on systems with non-4K pages. Reviewed-by:
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Alex Deucher authored
This fixes HDP flushes on systems with non-4K pages. Reviewed-by:
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Alex Deucher authored
This will be used to consolidate the register remap offset configuration and fix HDP flushes on systems non-4K pages. Reviewed-by:
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Alex Deucher authored
This will be used to consolidate the register remap offset configuration and fix HDP flushes on systems non-4K pages. Reviewed-by:
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Alex Deucher authored
This will be used to consolidate the register remap offset configuration and fix HDP flushes on systems non-4K pages. Reviewed-by:
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Alex Deucher authored
This will be used to consolidate the register remap offset configuration and fix HDP flushes on systems non-4K pages. Reviewed-by:
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Alex Deucher authored
This will be used to consolidate the register remap offset configuration and fix HDP flushes on systems non-4K pages. Reviewed-by:
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Alex Deucher authored
This will be used to consolidate the register remap offset configuration and fix HDP flushes on systems non-4K pages. Reviewed-by:
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Alex Deucher authored
This will be used to consolidate the register remap offset configuration and fix HDP flushes on systems non-4K pages. Reviewed-by:
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Alex Deucher authored
This will be used to consolidate the register remap offset configuration and fix HDP flushes on systems non-4K pages. Reviewed-by:
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Alex Deucher authored
This will be used to consolidate the register remap offset configuration and fix HDP flushes on systems non-4K pages. Reviewed-by:
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Alex Deucher authored
This will be used to consolidate the register remap offset configuration and fix HDP flushes on systems non-4K pages. Reviewed-by:
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Alex Deucher authored
Will be used to consolidate reg remap settings and fix HDP flushes on systems with non-4K pages. Reviewed-by:
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Alex Deucher authored
We don't get the right offset in that case. The GPU has an unused 4K area of the register BAR space into which you can remap registers. We remap the HDP flush registers into this space to allow userspace (CPU or GPU) to flush the HDP when it updates VRAM. However, on systems with >4K pages, we end up exposing PAGE_SIZE of MMIO space. Fixes: d8e408a8 ("drm/amdkfd: Expose HDP registers to user space") Reviewed-by:
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YiPeng Chai authored
Change log level. Signed-off-by:
YiPeng Chai <YiPeng.Chai@amd.com> Reviewed-by:
Yang Wang <kevinyang.wang@amd.com> Signed-off-by:
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Jesse Zhang authored
This patch enable UMD Pstates profile level for the renoir_set_performance_level interface. -profile_min_sclk -profile_min_fclk Signed-off-by:
Jesse Zhang <Jesse.Zhang@amd.com> Suggested-by:
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Likun Gao authored
Fix the coding error when load spl component for psp v14. Signed-off-by:
Likun Gao <Likun.Gao@amd.com> Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
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Tim Huang authored
Clear warning that using uninitialized variable r. Signed-off-by:
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Yang Wang authored
Fix null pointer issue when unload driver in SRIOV mode. Adjust the function position to ensure that the amdgpu_mca/aca_xxx_init() related functions can be initialized properly. Signed-off-by:
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Yang Wang authored
This patch is used to solve the problem of incorrect parsing of error counts. When the UE trigger gpu is reset, the driver will attempt to parse all possible ras blocks. For ras blocks that are not supported by the current ASIC, the driver should ignore this error. Signed-off-by:
Candice Li <candice.li@amd.com> Signed-off-by:
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Tim Huang authored
Clear warning that using uninitialized variable current_node. Signed-off-by:
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Tim Huang authored
Clear warning that using uninitialized variable index. Signed-off-by:
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Lin.Cao authored
In interrupt context, write dbg_ev_file will be run by work queue. It will cause write dbg_ev_file execution after debug_trap_disable, which will cause NULL pointer access. v2: cancel work "debug_event_workarea" before set dbg_ev_file as NULL. Signed-off-by:
Lin.Cao <lincao12@amd.com> Reviewed-by:
Jonathan Kim <jonathan.kim@amd.com> Signed-off-by:
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Ma Jun authored
Check the ring type value to fix the out-of-bounds write warning Signed-off-by:
Christian König <christian.koenig@amd.com> Reviewed-by:
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Lijo Lazar authored
Range of possible values of pdev_num is 0-63. Use int8_t as data type. That also fixes below warnings: >> drivers/gpu/drm/amd/amdxcp/amdgpu_xcp_drv.c:59:58: warning: '%d' >> directive output may be truncated writing between 1 and 11 bytes into >> a region of size 9 [-Wformat-truncation=] 59 | snprintf(dev_name, sizeof(dev_name), "amdgpu_xcp_%d", pdev_num); | ^~ drivers/gpu/drm/amd/amdxcp/amdgpu_xcp_drv.c:59:46: note: directive argument in the range [-2147483648, 63] 59 | snprintf(dev_name, sizeof(dev_name), "amdgpu_xcp_%d", pdev_num); | ^~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdxcp/amdgpu_xcp_drv.c:59:9: note: 'snprintf' output between 13 and 23 bytes into a destination of size 20 59 | snprintf(dev_name, sizeof(dev_name), "amdgpu_xcp_%d", pdev_num); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Fixes: 97d814fe ("drm/amd/amdxcp: Use unique name for partition dev") Signed-off-by:Lijo Lazar <lijo.lazar@amd.com> Reported-by:
kernel test robot <lkp@intel.com> Reviewed-by:
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Lijo Lazar authored
This reverts commit c37ce764. RCCL library is currently not treating spatial partitions differently, hence this change is causing issues. Revert temporarily till RCCL implementation is ready for spatial partitions. Signed-off-by:
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Ma Jun authored
Check the user input and phy_id value range to fix "Using uninitialized value phy_id" Signed-off-by:
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Ma Jun authored
Assign an default value to agc_btc_response in failed case Signed-off-by:
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Ma Jun authored
Check return value of smum_send_msg_to_smc to fix uninitialized variable varning Signed-off-by:
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Tim Huang authored
1. Fix a issue that using uninitialized mask to get the ultimate frequency. 2. Check return of smu_cmn_send_smc_msg_with_param to avoid using uninitialized variable residency. Signed-off-by:
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Jack Xiao authored
kiq ring test has overwitten ready flag, need disable after gfx hw init. Signed-off-by:
Jack Xiao <Jack.Xiao@amd.com> Acked-by:
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Lang Yu authored
Small APUs(i.e., consumer, embedded products) usually have a small carveout device memory which can't satisfy most compute workloads memory allocation requirements. We can't even run a Basic MNIST Example with a default 512MB carveout. https://github.com/pytorch/examples/tree/main/mnist. Error Log: "torch.cuda.OutOfMemoryError: HIP out of memory. Tried to allocate 84.00 MiB. GPU 0 has a total capacity of 512.00 MiB of which 0 bytes is free. Of the allocated memory 103.83 MiB is allocated by PyTorch, and 22.17 MiB is reserved by PyTorch but unallocated" Though we can change BIOS settings to enlarge carveout size, which is inflexible and may bring complaint. On the other hand, the memory resource can't be effectively used between host and device. The solution is MI300A approach, i.e., let VRAM allocations go to GTT. Then device and host can flexibly and effectively share memory resource. v2: Report local_mem_size_private as 0. (Felix) Signed-off-by:
Lang Yu <Lang.Yu@amd.com> Reviewed-by:
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Sunil Khatri authored
add the registers of SE block of gfx for ip dump for gfx10 IP. Signed-off-by:
Sunil Khatri <sunil.khatri@amd.com> Reviewed-by:
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Sunil Khatri authored
add registers in the ip dump for CP headers in gfx10 Signed-off-by:
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Mario Limonciello authored
Limit the workaround introduced by commit 31729e8c ("drm/amd/pm: fixes a random hang in S4 for SMU v13.0.4/11") to only run in the s4 path. Cc: Tim Huang <Tim.Huang@amd.com> Fixes: 31729e8c ("drm/amd/pm: fixes a random hang in S4 for SMU v13.0.4/11") Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/3351Signed-off-by:
Mario Limonciello <mario.limonciello@amd.com> Acked-by:
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