- 06 Dec, 2022 40 commits
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Manivannan Sadhasivam authored
Qualcomm platforms making use of CPUFreq HW Engine (EPSS/OSM) supply clocks to the CPU cores. But this relationship is not represented in DTS so far. So let's make cpufreq node as the clock provider and CPU nodes as the consumers. The clock index for each CPU node is based on the frequency domain index. Signed-off-by:
Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by:
Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221117053145.10409-3-manivannan.sadhasivam@linaro.org
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Bryan O'Donoghue authored
The Vision Mezzanine for the RB5 ships with an imx577 and ov9282 populated. Other sensors and components may be added or stacked with additional mezzanines. Enable the IMX577 on the vision mezzanine. An example media-ctl pipeline for the imx577 is: media-ctl --reset media-ctl -v -d /dev/media0 -V '"imx577 '22-001a'":0[fmt:SRGGB10/4056x3040 field:none]' media-ctl -V '"msm_csiphy2":0[fmt:SRGGB10/4056x3040]' media-ctl -V '"msm_csid0":0[fmt:SRGGB10/4056x3040]' media-ctl -V '"msm_vfe0_rdi0":0[fmt:SRGGB10/4056x3040]' media-ctl -l '"msm_csiphy2":1->"msm_csid0":0[1]' media-ctl -l '"msm_csid0":1->"msm_vfe0_rdi0":0[1]' yavta -B capture-mplane -c -I -n 5 -f SRGGB10P -s 4056x3040 -F /dev/video0 Reviewed-by:
Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by:
Bryan O'Donoghue <bryan.odonoghue@linaro.org> Signed-off-by:
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Bryan O'Donoghue authored
Define the set of possible ports, one for each CSI PHY along with the port address and size cells @ the SoC dtsi level. Suggested-by:
Konrad Dybcio <konrad.dybcio@somainline.org> Suggested-by:
Laurent Pinchart <laurent.pinchart@ideasonboard.com> Reviewed-by:
Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org> Reviewed-by:
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Bryan O'Donoghue authored
Move the dts data for the rb3 navigation mezzanine into its own dts file. Suggested-by:
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by:
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Bryan O'Donoghue authored
Use preferred "ok" not "okay". Use preferred status "disabled" instead of "disable". There's no functional change here so no Fixes has been applied. Reported-by:
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Bryan O'Donoghue authored
The reg for the port is specified in the dtsi. Remove from the db845c dts. Reviewed-by:
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Bryan O'Donoghue authored
sdm845.dtsi camss already defines the address-cells and size-cells for camss, no need to replicate in sdm845-db845c.dts. Reported-by:
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Bryan O'Donoghue authored
The number of available ports is SoC specific so we should define it in the SoC dtsi. For the case of the sdm845 that is 4 CSI PHYs => four ports. Reviewed-by:
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Konrad Dybcio authored
Adjust regulators, add required pin setup and finally enable SDHCI2 to get the SD Card slot going on Sagami Xperias. Signed-off-by:
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Konrad Dybcio authored
Sony ever so graciously provides GPIO line names in their downstream kernel (though sometimes they are not 100% accurate and you can judge that by simply looking at them and with what drivers they are used). Add these to the Sagami-common / PDX215 DTSIs to better document the hardware. Diff between 215 and common: < "NC", < "NC", > "WLC_I2C_SDA", > "WLC_I2C_SCL", < "NC", > "WLC_INT_N", > "CAM_MCLK4", < "NC", < "NC", > "TOF_RST_N", < "NC", < "NC", < "NC", > "QLINK1_REQ", > "QLINK1_EN", > "QLINK1_WMSS_RESET_N", It's pretty logical as 1 III has WLC (WireLess Charging), and an additional 3D iToF sensor. As for QLINK, no idea. Signed-off-by:
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Konrad Dybcio authored
Add and configure the SDHCI host responsible for (mostly) SD Card and its corresponding pins' sleep states. The setup is *literally* 1:1 with 8450 (bar SDR50/104 may not be broken). Signed-off-by:
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Johan Hovold authored
When recently adding the missing 'regulator-allowed-modes' properties it appears that the binding example with its four-spaces indentation (corresponding to a single tab, which is still to little) was copied verbatim. Drop the unnecessary first line break after 'regulator-allowed-modes' properties and indent the single remaining continuation line properly. Signed-off-by:
Johan Hovold <johan+linaro@kernel.org> Reviewed-by:
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Srinivasa Rao Mandadapu authored
Remove unused and redundant sleep pin control entries as they are not referenced anywhere in sc7280 based platform's device tree variants. Signed-off-by:
Srinivasa Rao Mandadapu <quic_srivasam@quicinc.com> Reported-by:
Douglas Anderson <dianders@chromium.org> Reviewed-by:
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by:
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Konrad Dybcio authored
PMK8350 is the first PMIC to require both HLOS and PBS registers for PON to function properly (at least in theory, sm8350 sees no change). The support for it on the driver side has been added long ago, but it has never been wired up. Do so. Signed-off-by:
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Konrad Dybcio authored
Use the defines from qcom-rpmpd.h instead of bare numbers for readability. Signed-off-by:
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Konrad Dybcio authored
Use the defines from qcom-rpmpd.h instead of bare numbers for readability. Signed-off-by:
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Konrad Dybcio authored
Enable the newly added remote processors and assign them a firmware path. Signed-off-by:
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Konrad Dybcio authored
Add ADSP & CDSP remote processors. Signed-off-by:
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Konrad Dybcio authored
Add nodes for ADSP&CDSP SMP2P. Signed-off-by:
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Konrad Dybcio authored
Set SDHCI VMMC/VQMMC to <=2v96 and allow load setting by the SDHCI driver, as required by this use case. Configure the SD Card Detect pin, enable the SDHCI2 controller and assign it the aforementioned regulators. Signed-off-by:
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Konrad Dybcio authored
Add a pretty bog-standard-for-Xperias-for-the-past-3-years touchscreen setup. The OEM that built the Xperia 10 IV for SONY decided to use some kind of a GPIO regulator that needs to be enabled at all times for both the touch panel and the display panel to function. Signed-off-by:
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Konrad Dybcio authored
Configure regulators present on the Xperia 10 IV that are reachable via SMD RPM. Signed-off-by:
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Konrad Dybcio authored
Add and enable PMIC peripherals for PM6125, PMR735a and PMK8350 on the Xperia 10 IV. Signed-off-by:
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Konrad Dybcio authored
Enable QUPs & GPI DMA on the Xperia 10 IV. Signed-off-by:
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Konrad Dybcio authored
Configure the second SDHCI bus controller, which usually the interface used for SD cards. Reviewed-by:
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Konrad Dybcio authored
Add necessary nodes to support various QUP configurations. Note that: - QUP3/4/5 and 11 are straight up missing - There may be more QUPs physically on the SoC that work perfectly fine, but Qualcomm decided not to expose them on the downstream kernel - Many are missing pinctrls, as there are both missing pin funcs in the TLMM driver and missing configuration settings (though they are possible to guesstimate quite easily) Signed-off-by:
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Konrad Dybcio authored
Add the pin setup for SPI/I2C configurations that are supported downstream. I can guesstimate the correct settings for other buses, but: - I have no hardware to test it on - Some QUPs are straight up missing pin funcs in TLMM - Vendors probably didn't really care and used whatever was there in the reference design and BSP - should any other be used, they can be configured at a later time Acked-by:
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Konrad Dybcio authored
Add nodes for GPI DMA hosts on SM6375. Signed-off-by:
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Konrad Dybcio authored
PMK8350 is shipped on SID6 with some SoCs, for example with SM6375. Add some preprocessor logic to allow changing the SID in cases like this. While I am not in favour of adding #if's into the device tree, this is the least messy way to handle this. If one isn't specified, it will default to 0 (as it has been previously). Suggested-by:
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Konrad Dybcio authored
Add device node and required pinctrl settings (as well as a fixup for an existing one, whoops!) to support the Samsung Electronics touchscreen on Nagara devices. Signed-off-by:
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Konrad Dybcio authored
Add a device tree for the Xperia 5 IV (pdx224). It's literally the 1 IV with a smaller body, different panel, one camera lens (not sensor afaict) swapped out and no 3D iToF sensor, hence the device-specific DT is tiny. Be sure to follow the vbmeta disablement steps (detailed in pdx223 introduction commit message), otherwise your phone will not boot and will reject anything and everything with just a non-descriptive "Your device is corrupted" followed by a sad reboot. This should not be the case, as vbmeta should be plainly ignored in unlocked state, but what can we do.. Signed-off-by:
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Konrad Dybcio authored
Turns out 1 IV is not the only Nagara device, reflect that in the DTS. Signed-off-by:
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Mao Jinlong authored
Add coresight components for sm8250. STM/ETM are added. Signed-off-by:
Tao Zhang <quic_taozha@quicinc.com> Signed-off-by:
Mao Jinlong <quic_jinlmao@quicinc.com> Signed-off-by:
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Dzmitry Sankouski authored
New device support - Xiaomi Mi6 phone What works: - storage - usb - power regulators Signed-off-by:
Dzmitry Sankouski <dsankouski@gmail.com> Reviewed-by:
Konrad Dybcio <konra.dybcio@linaro.org> Signed-off-by:
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AngeloGioacchino Del Regno authored
This adds support for the Sony Xperia Loire/SmartLoire platform with a base configuration that is common across all of the devices that are based on this project. Also adds a base DT configuration for the Xperia X and Xperia X Compact (respectively, Suzu and Kugo) which is valid for both their RoW (single-sim), DSDS (dual-sim) and other regional variants of these two smartphones, that makes us able to boot to a UART console. Please note that, currently, the APC0/1 (cluster 0/1) vregs are set to a safe voltage in order to ensure boot stability until a proper solution for CPU DVFS scaling lands. Co-developed-by:
Marijn Suijten <marijn.suijten@somainline.org> Signed-off-by:
AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by:
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AngeloGioacchino Del Regno authored
This commit adds device trees for MSM8956 and MSM8976 SoCs. They are *almost* identical, with minor differences, such as MSM8956 having two A72 cores less. However, there is a bug in Sony Loire bootloader that requires presence of all 8 cores in the cpu{} node, so these will not be deleted. Co-developed-by: -
AngeloGioacchino Del Regno authored
The PMI8950 features integrated peripherals like ADC, GPIO controller, MPPs and others. [luca@z3ntu.xyz: remove pm8950, style changes for 2022 standards, add wled] Signed-off-by:
AngeloGioacchino Del Regno <kholk11@gmail.com> Signed-off-by:
Luca Weiss <luca@z3ntu.xyz> Signed-off-by:
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AngeloGioacchino Del Regno authored
The PM8950 features integrated peripherals like ADC, GPIO controller, MPPs, PON keys and others. Add them to DT files that will be imported on boards having this PMIC combo (or one of them, anyways). Signed-off-by:
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Johan Hovold authored
When adding support for the DisplayPort part of the QMP PHY the binding (and devicetree parser) for the (USB) child node was simply reused and this has lead to some confusion. The third DP register region is really the DP_PHY region, not "PCS" as the binding claims, and lie at offset 0x2a00 (not 0x2c00). Similarly, there likely are no "RX", "RX2" or "PCS_MISC" regions as there are for the USB part of the PHY (and in any case the Linux driver does not use them). Note that the sixth "PCS_MISC" region is not even in the binding. Fixes: 5aa0d1be ("arm64: dts: qcom: sm8250: switch usb1 qmp phy to USB3+DP mode") Cc: stable@vger.kernel.org # 5.13 Signed-off-by:
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Johan Hovold authored
When adding support for the DisplayPort part of the QMP PHY the binding (and devicetree parser) for the (USB) child node was simply reused and this has lead to some confusion. The third DP register region is really the DP_PHY region, not "PCS" as the binding claims, and lie at offset 0x2a00 (not 0x2c00). Similarly, there likely are no "RX", "RX2" or "PCS_MISC" regions as there are for the USB part of the PHY (and in any case the Linux driver does not use them). Note that the sixth "PCS_MISC" region is not even in the binding. Fixes: 23737b95 ("arm64: dts: qcom: sm6350: Add USB1 nodes") Cc: stable@vger.kernel.org # 5.16 Signed-off-by:
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