- 11 Oct, 2017 2 commits
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Chen-Yu Tsai authored
All the A31/A31s devices I own have some kind of HDMI connector wired to the dedicated HDMI pins on the SoC: - A31 Hummingbird (standard HDMI connector, display already enabled) - Sinlinx SinA31s (standard HDMI connector) - MSI Primo81 tablet (micro HDMI connector) Enable the display pipeline (if needed) and HDMI output for them. Signed-off-by:
Chen-Yu Tsai <wens@csie.org> Signed-off-by:
Maxime Ripard <maxime.ripard@free-electrons.com>
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Chen-Yu Tsai authored
Now that we support the HDMI controller on the A31 SoC, we can add it to the device tree. This adds a device node for the HDMI controller, and the of_graph nodes connecting it to the 2 TCONs. Signed-off-by:
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- 09 Oct, 2017 3 commits
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Maxime Ripard authored
One of the usage of the LRADC is to implement buttons. The bindings define that we should have one subnode per button, with their associated voltage as a property. However, there was no reg property but we still used the voltage associated to the button as the unit-address, which eventually generated warnings in DTC. Rename the node names to avoid those warnings. Signed-off-by: -
Maxime Ripard authored
Using skeleton.dtsi will create a memory node that will generate a warning in DTC. However, that node will be created by the bootloader, so we can just remove it entirely in order to remove that warning. Acked-by:
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Maxime Ripard authored
Some gpio-keys definitions in our DTs were having buttons defined with a unit-address and that would generate a DTC warning. Change the buttons node names to remove the warnings. Acked-by:
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- 06 Oct, 2017 15 commits
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Maxime Ripard authored
The board has an external pull-up on the card-detect signal, so there's no need to add another one. This also removes a DTC warning. Acked-by:
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Maxime Ripard authored
The board has an external pull-up on the card-detect signal, so there's no need to add another one. This also removes a DTC warning. Acked-by:
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Maxime Ripard authored
Our pinctrl node names were containing unit-adresses without a reg property, resulting in a warning. Change the names for our new convention. Acked-by:
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Maxime Ripard authored
The A80 boards still define some GPIO pinctrl nodes that are not really useful, and redundant with the muxing already happening on gpio_request. Let's remove those nodes. This will also remove DTC warnings. Acked-by:
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Maxime Ripard authored
Using skeleton.dtsi will create a memory node that will generate a warning in DTC. However, that node will be created by the bootloader, so we can just remove it entirely in order to remove that warning. Acked-by:
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Maxime Ripard authored
The gpio pinctrl nodes are redundant and as such useless most of the times. Since they will also generate warnings in DTC, we can simply remove most of them. Acked-by:
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Maxime Ripard authored
The thermal-zone subnodes we defined for the A10 have underscores in them that will generate DTC warnings. Change those underscores for hyphens. Acked-by:
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Maxime Ripard authored
Our main node for all the in-SoC controllers used to have a unit name. The unit-name, in addition to being actually false, would not match any reg property, which generates a warning. Remove it in order to remove those warnings. Acked-by:
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Maxime Ripard authored
Our oscillators clock names have a unit address, but no reg property, which generates a warning in DTC. Change these names to remove those unit addresses. Acked-by:
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Maxime Ripard authored
The simple-framebuffer nodes have a unit address, but no reg property which generates a warning when compiling it with DTC. Change the simple-framebuffer node names so that there is no warnings on this anymore. Acked-by:
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Maxime Ripard authored
The USB power supply node in the AXP209 DTSI is using underscores in its node name, which is generating a warning. Change those underscores for hyphens. Acked-by:
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Maxime Ripard authored
Most of our device trees have had leading zeros for padding as part of the nodes unit-addresses. Remove all these useless zeros that generate warnings Acked-by:
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Icenowy Zheng authored
The Banana Pi M2 Ultra is an SBC based on the Allwinner V40 SoC (same as the R40 SoC). The form factor is similar to the Raspberry Pi series. It features: - X-Powers AXP221s PMIC connected to i2c0 - 1GiB DDR3 DRAM - microSD slot - MicroUSB Type-B port for power and connected to usb0 - HDMI output - MIPI DSI connector - 4 USB Type-A ports (connected to the usb1 controller via a hub) - gigabit ethernet with Realtek RTL8211E transceiver - WiFi/Bluetooth with AP6212 module, with external antenna connector - SATA and power connectors for native SATA support - camera sensor connector - audio out headphone jack - red and green LEDs - debug UART pins - Raspberry Pi B+ compatible GPIO header - power and reset buttons This patch adds a dts file that enables UART, MMC and PMIC support. Signed-off-by:
Icenowy Zheng <icenowy@aosc.io> Signed-off-by:
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Chen-Yu Tsai authored
The Banana Pi M2 Ultra is an SBC based on the Allwinner R40 SoC. The form factor and position of various connectors, leds and buttons is similar to the Banana Pi M1+, Banana Pi M3, and is exactly the same as the latest Banana Pi M64. It features: - X-Powers AXP221s PMIC connected to i2c0 - 2 GB DDR3 DRAM - 8 GB eMMC - micro SD card slot - DC power jack - HDMI output - MIPI DSI connector - 2x USB 2.0 hosts - 1x USB 2.0 OTG - gigabit ethernet with Realtek RTL8211E transceiver - WiFi/Bluetooth with AP6212 chip, with external antenna connector - SATA and power connectors for native SATA support - camera sensor connector - consumer IR receiver - audio out headphone jack - onboard microphone - red, green, and blue LEDs - debug UART pins - Li-Po battery connector - Raspberry Pi B+ compatible GPIO header - power, reset, and boot control buttons This patch adds a dts file that enables UART, MMC and PMIC support. Signed-off-by:
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Chen-Yu Tsai authored
The Allwinner R40 SoC is marketed as the successor to the A20 SoC. The R40 is a smaller chip than the A20, but features the same set of programmable pins, with a couple extra pins and some new pin functions. The chip features 4 Cortex-A7 cores and a Mali-400 MP2 GPU. It retains most if not all features from the A20, while adding some new features, such as MIPI DSI output, or updating various hardware blocks, such as DE 2.0. Signed-off-by:
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- 27 Sep, 2017 2 commits
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Corentin LABBE authored
This patch remove leading 0 of unit address and so remove lots of warning when building DT with W=1. Signed-off-by:
Corentin Labbe <clabbe.montjoie@gmail.com> Acked-by:
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Corentin LABBE authored
This patch fixes the warning "xxx has a unit name, but no reg property" by removing "@0" from such node. 6 board files are fixed. Each has the same aforementioned issue in pinmux nodes. These include the Nano Pi family base dtsi file, the Orange Pi 2, Orange Pi Lite, Orange Pi One, Orange Pi PC, and Orange Pi Plus. Signed-off-by:
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- 26 Sep, 2017 3 commits
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Corentin LABBE authored
This patch fix the warning "xxx has a unit name, but no reg property" by removing "@0" from such node. Signed-off-by:
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Corentin LABBE authored
The unit address and register address does not match. This patch fix the register address with the good one. Acked-by:
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Corentin LABBE authored
This patch remove leading 0 of unit address and so remove lots of warning when building DT with W=1. Signed-off-by:
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- 17 Sep, 2017 15 commits
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Icenowy Zheng authored
The Lamobo R1 board connected the ACIN of the AXP209 PMIC to a MicroUSB port, and the battery input is connected to a generic connector. Enable these two power supplies in the device tree. Signed-off-by:
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Chen-Yu Tsai authored
The TCONs on A31/A31s can select either backend as its input. As there is no configurable mux in the backend or DRC to redirect their output, or for the DRC to select an input, the connections are presumably from the each DRC to each TCON, with the TCON having two input ports, like the following diagram: Backend 0 ------- DRC 0 ------- [0] TCON 0 -- -- [1] \ / X / \ -- -- [0] Backend 1 ------- DRC 1 ------- [1] TCON 1 Add these connection endpoints to the device tree. Signed-off-by: -
Philipp Rossak authored
There is no need for pincontrol nodes when the pin is set to a GPIO Signed-off-by:
Philipp Rossak <embed3d@gmail.com> Signed-off-by:
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Marcus Cooper authored
Add the new DAI blocks to the device tree. I2S0 and I2S1 are for connecting to an external codec. Signed-off-by:
Marcus Cooper <codekipper@gmail.com> Signed-off-by:
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Philipp Rossak authored
The WiFi side of the AP6212 WiFi/BT combo module is connected to mmc1. There are also GPIOs for enable and interrupts. Enable WiFi on this board by enabling mmc1 and adding the power sequencing clocks and GPIO, as well as the chip's interrupt line. Signed-off-by:
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Maxime Ripard authored
The TBS A711 is a tablet with an A83T, a modem, wifi/BT chip, an eMMC and a 1024x600 LVDS display. Reviewed-by:
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Priit Laes authored
sun4i-a10.dtsi was missing i2s0 block. Add it. Signed-off-by:
Priit Laes <plaes@plaes.org> Signed-off-by:
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Marcus Cooper authored
Add the new DAI blocks to the device tree. Signed-off-by:
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Maxime Ripard authored
The A83T has an UART1 controller, with the RTS and CTS pins routed so it can be used for devices with hardware flow control, like a bluetooth chip. Acked-by:
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Maxime Ripard authored
Add the pinctrl definitions for the A83t MMC1 controller. Acked-by:
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Maxime Ripard authored
Those nodes are useless, remove them. Acked-by:
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Tomas Novotny authored
TBS is a company providing biometrics products and solution in Access control and time management. Signed-off-by:
Tomas Novotny <tomas@novotny.cz> Acked-by:
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Stefan Mavrodiev authored
From revision J the board uses new phy chip LAN8710. Compared with RTL8201, RA17 pin is TXERR. It has pullup which causes phy not to work. To fix this PA17 is muxed with GMAC function. This makes the pin output-low. This patch is compatible with earlier board revisions, since this pin wasn't connected to phy. Signed-off-by:
Stefan Mavrodiev <stefan@olimex.com> Signed-off-by:
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Philipp Rossak authored
The BT side of the AP6212 WiFi/BT combo module is connected to uart3. Enable BT on this board by enabling uart3 with using additionally the cts and rts pins. Signed-off-by:
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Philipp Rossak authored
This node adds the definition for the UART3 RTS and CTS Pins That makes it able to use UART3 with RTS and CTS. Signed-off-by:
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