- 22 Aug, 2019 12 commits
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Kuninori Morimoto authored
It might return without initializing in error case. In such case, uninitialized variable might be used at error handler. This patch initializes all necessary variable before return. Signed-off-by:
Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Reviewed-by:
Ranjani Sridharan <ranjani.sridharan@linux.intel.com> Link: https://lore.kernel.org/r/87zhk4zazt.wl-kuninori.morimoto.gx@renesas.comSigned-off-by:
Mark Brown <broonie@kernel.org>
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Kuninori Morimoto authored
commit 52abe6cc ("ASoC: topology: fix oops/use-after-free case with dai driver") fixups remove_dai() error, but it is using list_for_each_entry() for component->dai_list. We already have for_each_component_dais() macro for it. Let's use exising method. Signed-off-by:
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Kuninori Morimoto authored
.bus_control can be bit field. this patch do it. Signed-off-by:
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Kuninori Morimoto authored
There is no need to check return value for soc_cleanup_card_resources(). Let't makes it as void. Signed-off-by:
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Kuninori Morimoto authored
We can find specified name component via snd_soc_rtdcom_lookup(). But, it is not enough under multi CPU/Codec/Platform, because many components which have same driver name might be connected to same rtd. Not using this function as much as possible is best solution, but some drivers are already deeply depended to it. We can expand this function, for example having "num" which specifies found order at parameter, etc (In such case, it need to have fixed probing order). Or, use different driver name in such component, etc. We will have such issue if multi CPU/Codec/Platform were supported. To indicate it, this patch adds NOTE to this function. Signed-off-by:
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Kuninori Morimoto authored
It is easy to read code if it is cleanly using paired function/naming, like start <-> stop, register <-> unregister, etc, etc. But, current ALSA SoC code is very random, unbalance, not paired, etc. soc-core.c is using device_unregiser(), but there is no its paired device_regiser(). We can find its code at soc_post_component_init() which is using device_initialize() and device_add(). Here, device_initialize() + device_add() = device_register(). -- linux/drivers/base/core.c -- int device_register(struct device *dev) { device_initialize(dev); return device_add(dev); } device_initialize() is doing each dev member's initialization only, not related to device parent/release/groups. Thus, we can postpone it. let's use device_register() instead of device_initialize()/device_add(). Signed-off-by: -
Jiaxin Yu authored
Pull TDM pins down when TDM BE shutdown to avoid current leakage. Signed-off-by:
Jiaxin Yu <jiaxin.yu@mediatek.com> Link: https://lore.kernel.org/r/1566478261-13464-2-git-send-email-jiaxin.yu@mediatek.comSigned-off-by:
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YueHaibing authored
sound/soc/mediatek/mt2701/mt2701-afe-common.h:66:27: warning: mt2701_afe_backup_list defined but not used [-Wunused-const-variable=] mt2701_afe_backup_list is only used in mt2701-afe-pcm.c, so just move the definition over there. Reported-by:
Hulk Robot <hulkci@huawei.com> Signed-off-by:
YueHaibing <yuehaibing@huawei.com> Link: https://lore.kernel.org/r/20190822143747.20944-1-yuehaibing@huawei.comSigned-off-by:
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YueHaibing authored
sound/soc/codecs/wm8988.c:270:30: warning: wm8988_rline_enum defined but not used [-Wunused-const-variable=] wm8988_rline_enum should be used in wm8988_right_line_controls. Reported-by:
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Daniel Baluta authored
Add support for the audio DSP hardware found on NXP i.MX8 platform. Signed-off-by:
Daniel Baluta <daniel.baluta@nxp.com> Signed-off-by:
Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com> Link: https://lore.kernel.org/r/20190821164730.7385-4-pierre-louis.bossart@linux.intel.comSigned-off-by:
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Daniel Baluta authored
Add support for device tree based SOF DSP devices. Signed-off-by:
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Daniel Baluta authored
This describes the DSP device tree node. Signed-off-by:
Rob Herring <robh@kernel.org> Signed-off-by:
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- 21 Aug, 2019 9 commits
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Maxime Ripard authored
In addition to the I2S format, the controller also supports the DSP_* formats. This requires some extra care on the LRCK period calculation, since the controller, with the PCM formats, require that the value set is no longer the periods of LRCK for a single channel, but for all of them. Let's add the code to deal with this, and support the DSP_A and DSP_B formats. Signed-off-by:
Maxime Ripard <maxime.ripard@bootlin.com> Link: https://lore.kernel.org/r/5562db1ac8759f12b1b87c3258223eed629ef771.1566392800.git-series.maxime.ripard@bootlin.comSigned-off-by:
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Maxime Ripard authored
The sun4i_i2s_hw_params function already has a variable holding the value returned by params_width, so let's just use that variable instead of calling params_width multiple times. Signed-off-by:
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Maxime Ripard authored
The LRCK period field in the FMT0 register holds the number of LRCK period for one channel in I2S mode. This has been hardcoded to 32, while it really should be the physical width of the format, which creates an improper clock when using a 16bit format, with the i2s controller as LRCK master. Fixes: 7d299381 ("ASoC: sun4i-i2s: Add support for H3") Signed-off-by:
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Maxime Ripard authored
The clock dividers function has been using the word size to compute the clock rate at which it's supposed to be running, but the proper formula would be to use the physical width and / or slot width in TDM. It doesn't make any difference at the moment since all the formats supported have the same sample width and physical width, but it's not going to last forever. Fixes: 7d299381 ("ASoC: sun4i-i2s: Add support for H3") Signed-off-by:
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Maxime Ripard authored
The i2s controller supports TDM, for up to 8 slots. Let's support the TDM API. Signed-off-by:
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Kuninori Morimoto authored
snd_soc_remove_dai_link() has card connected dai_link check. but 1) we need to call list_del() anyway, because it is "remove" function, 2) It is doing many thing for this card / dai_link already before checking dai_link. This patch removes poinless dai_link check Signed-off-by:
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Kuninori Morimoto authored
snd_soc_initialize_card_lists() is doing card related INIT_LIST_HEAD(), but, it is already doing at snd_soc_register_card(). We don't need to do it separately. This patch merges these. Signed-off-by:
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Daniel Baluta authored
Register map for i.MX8QM is similar with i.MX6 series. Integration of SAI IP into i.MX8QM SOC features a FIFO size of 64 X 32 bits samples. Signed-off-by:
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Daniel Baluta authored
SAI module on imx8qm features a register map similar with imx6 series (it doesn't have VERID and PARAM registers at the beginning of address spece). Also, it has one FIFO which can help up to 64 * 32 bit samples. Signed-off-by:
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- 20 Aug, 2019 19 commits
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Codrin Ciubotariu authored
This controller supports capture and playback running at the same time, with the limitation that both capture and playback must be configured the same way (sample rate, sample format, number of channels, etc). For this, we have to assure that the configuration registers look the same when capture and playback are initiated. This patch fixes a bug in which the controller is in master mode and the hw_params() callback fails for the second audio stream. The fail occurs because the divisors are calculated after comparing the configuration registers for capture and playback. The fix consists in calculating the divisors before comparing the configuration registers. BCLK and LRC are then configured and started only if the controller is not already running. Fixes: 7e0cdf545a55 ("ASoC: mchp-i2s-mcc: add driver for I2SC Multi-Channel Controller") Signed-off-by:Codrin Ciubotariu <codrin.ciubotariu@microchip.com> Link: https://lore.kernel.org/r/20190820162411.24836-4-codrin.ciubotariu@microchip.comSigned-off-by:
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Maxime Ripard authored
We've been limited to 2 channels in the driver while the controller supports from 1 to 8 channels, in both capture and playback. let's remove the hardcoded checks and numbers, and extend the range of channel numbers we can use. Signed-off-by:
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Maxime Ripard authored
The channels number have been hardcoded to 2 so far, while the controller supports more than that. Remove the instance where it has been hardcoded to compute the BCLK divider, and pass it through as an argument to ease further support of more channels. Signed-off-by:
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Maxime Ripard authored
The A83t and H3 have the same quirks, so it doesn't make sense to duplicate the quirks structure. Signed-off-by:
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Maxime Ripard authored
Unlike the previous SoCs, the A83t, like the newer ones, need the LRCK bitfield to be set. Let's add it. Fixes: 21faaea1 ("ASoC: sun4i-i2s: Add support for A83T") Signed-off-by:
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Maxime Ripard authored
The A83t, unlike previous SoCs, has the MCLK enable bit at the 8th bit of the CLK_DIV register, unlike what is declared in the driver. Fixes: 21faaea1 ("ASoC: sun4i-i2s: Add support for A83T") Signed-off-by:
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Maxime Ripard authored
The A83t has the same bit fields offsets than the A10 and A31, while this was the first device with the new layout, fix that. Fixes: 21faaea1 ("ASoC: sun4i-i2s: Add support for A83T") Signed-off-by:
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Maxime Ripard authored
The LRCK polarity "normal" polarity in the I2S/TDM specs and in the Allwinner datasheet are not the same. In the case where the i2s controller is being used as the LRCK master, it's pretty clear when looked at under a scope. Let's fix this, and add a comment to clear up as much the confusion as possible. Fixes: 7d299381 ("ASoC: sun4i-i2s: Add support for H3") Fixes: 21faaea1 ("ASoC: sun4i-i2s: Add support for A83T") Signed-off-by:
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Maxime Ripard authored
The LRCK and BCLK polarity offsets on newer SoCs has been changed, yet the driver didn't take it into account for all of them. This was taken into account for the H3, but not the A83t. This was handled using a reg_field for the H3. However, the value in that field will not be the same, so reg_field is not adapted in that case. Let's change for proper calls with the regular values. Fixes: 21faaea1 ("ASoC: sun4i-i2s: Add support for A83T") Signed-off-by:
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Maxime Ripard authored
The RX and TX counters registers offset have been swapped, fix that. Fixes: fa7c0d13 ("ASoC: sunxi: Add Allwinner A10 Digital Audio driver") Signed-off-by:
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Maxime Ripard authored
From: Marcus Cooper <codekipper@gmail.com> The clock division dividers have changed between the older (A10/A31) and newer (H3, A64, etc) SoCs. While this was addressed through an offset on some SoCs, it was missing some dividers as well, so the support wasn't perfect. Let's introduce a pointer in the quirk structure for the divider calculation functions to use so we can have the proper range now. Signed-off-by:
Marcus Cooper <codekipper@gmail.com> [Maxime: Fix the commit log, use a field in the quirk structure] Signed-off-by:
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Maxime Ripard authored
On the first generation of Allwinner SoCs (A10-A31), the i2s controller was using the MCLK as BCLK parent. However, this changed since the introduction of the A83t and BCLK now uses the module clock as its parent. Let's introduce a hook to get the parent rate and use that in our divider calculations. Fixes: 7d299381 ("ASoC: sun4i-i2s: Add support for H3") Fixes: 21faaea1 ("ASoC: sun4i-i2s: Add support for A83T") Signed-off-by:
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Maxime Ripard authored
The two main generations of our I2S controller require a slightly different format configuration, mostly because of a quite different register layout and some additional registers being needed on the newer generation. This used to be controlled through a bunch of booleans, however this proved to be quite impractical, especially since a bunch of SoCs forgot to set those parameters and therefore were broken from that point of view. Fixes: 21faaea1 ("ASoC: sun4i-i2s: Add support for A83T") Signed-off-by:
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Maxime Ripard authored
The two main generations of our I2S controller require a slightly different channel configuration, mostly because of a quite different register layout and some additional registers being needed on the newer generation. This used to be controlled through a bunch of booleans, however this proved to be quite impractical, especially since a bunch of SoCs forgot to set those parameters and therefore were broken from that point of view. Fixes: 21faaea1 ("ASoC: sun4i-i2s: Add support for A83T") Signed-off-by:
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Mark Brown authored
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Daniel Stuart authored
Every single baytrail chromebook sets PMC to 0, as can be seeing below by searching through coreboot source code: $ grep -rl "PMC_PLT_CLK\[0\]" . ./rambi/variants/glimmer/devicetree.cb ./rambi/variants/clapper/devicetree.cb ./rambi/variants/swanky/devicetree.cb ./rambi/variants/enguarde/devicetree.cb ./rambi/variants/winky/devicetree.cb ./rambi/variants/kip/devicetree.cb ./rambi/variants/squawks/devicetree.cb ./rambi/variants/orco/devicetree.cb ./rambi/variants/ninja/devicetree.cb ./rambi/variants/heli/devicetree.cb ./rambi/variants/sumo/devicetree.cb ./rambi/variants/banjo/devicetree.cb ./rambi/variants/candy/devicetree.cb ./rambi/variants/gnawty/devicetree.cb ./rambi/variants/rambi/devicetree.cb ./rambi/variants/quawks/devicetree.cb Plus, Cyan (only non-baytrail chromebook with max98090) also needs this patch for audio to work. Thus, this commit adds all the missing devices to bsw_max98090 quirk table, implemented by commit a182ecd3 ("ASoC: intel: cht_bsw_max98090_ti: Add quirk for boards using pmc_plt_clk_0"). Signed-off-by:
Daniel Stuart <daniel.stuart14@gmail.com> Link: https://lore.kernel.org/r/20190815171300.30126-1-daniel.stuart14@gmail.comSigned-off-by:
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Maxime Ripard authored
The MCLK divider calculation is currently computing the ideal divider using the oversample rate, the sample rate and the parent rate. However, since we have access to the frequency is supposed to be running at already, and as it turns out we're using it to compute the oversample rate, we can just use the ratio between the parent rate and the MCLK rate to simplify a bit the formula. Signed-off-by:
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Maxime Ripard authored
The sun4i_i2s_hw_params already has a variable holding the value returned by params_channels, so let's just use that variable instead of calling params_channels multiple times. Signed-off-by:
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Maxime Ripard authored
The BCLK divider should be calculated using the parameters that actually make the BCLK rate: the number of channels, the sampling rate and the sample width. We've been using the oversample_rate previously because in the former SoCs, the BCLK's parent is MCLK, which in turn is being used to generate the oversample rate, so we end up with something like this: oversample = mclk_rate / sampling_rate bclk_div = oversample / word_size / channels So, bclk_div = mclk_rate / sampling_rate / word_size / channels. And this is actually better, since the oversampling ratio only plays a role because the MCLK is its parent, not because of what BCLK is supposed to be. Furthermore, that assumption of MCLK being the parent has been broken on newer SoCs, so let's use the proper formula, and have the parent rate as an argument. Fixes: 7d299381 ("ASoC: sun4i-i2s: Add support for H3") Fixes: 21faaea1 ("ASoC: sun4i-i2s: Add support for A83T") Fixes: 66ecce33 ("ASoC: sun4i-i2s: Add compatibility with A64 codec I2S") Signed-off-by:
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