- 05 May, 2022 5 commits
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Mike Lothian authored
This stops clang complaining: drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c:3846:6: warning: variable 'index' is used uninitialized whenever 'if' condition is true [-Wsometimes-uninitialized] if (ring->is_mes_queue) { ^~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c:3903:30: note: uninitialized use occurs here amdgpu_device_wb_free(adev, index); ^~~~~ drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c:3846:2: note: remove the 'if' if its condition is always false if (ring->is_mes_queue) { ^~~~~~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c:3839:16: note: initialize the variable 'index' to silence this warning unsigned index; ^ = 0 Signed-off-by:Mike Lothian <mike@fireburn.co.uk> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Mike Lothian authored
This stops clang complaining: drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c:5895:2: warning: unannotated fall-through between switch labels [-Wimplicit-fallthrough] default: ^ drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c:5895:2: note: insert 'break;' to avoid fall-through default: ^ break; Signed-off-by: -
Alex Deucher authored
This reverts commit 9a45ac23. This was added a helper for amdgpu to workaround a runtime pm regression caused by a runtime pm fix in efifb. We now have a better workaround in amdgpu in commit f95af4a9 ("drm/amdgpu: don't runtime suspend if there are displays attached (v3)") so this workaround is no longer necessary. Since amdgpu was the only user of this interface, we can remove it. Reviewed-by:
Javier Martinez Canillas <javierm@redhat.com> Acked-by:
Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by:
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Alex Deucher authored
This reverts commit b95dc06a. This workaround is no longer necessary. We have a better workaround in commit f95af4a9 ("drm/amdgpu: don't runtime suspend if there are displays attached (v3)"). Reviewed-by:
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Alex Deucher authored
Some copy paste leftovers for older asics. They were protected by __BIG_ENDIAN, so we didn't notice them initially. Reported-by:
kernel test robot <lkp@intel.com> Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
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- 04 May, 2022 35 commits
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James Zhu authored
Enable VCN 4.0 on asics where it is present. Signed-off-by:
James Zhu <James.Zhu@amd.com> Signed-off-by:
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James Zhu authored
Add vcn_4_0_0 video codec query. Signed-off-by:
Leo Liu <leo.liu@amd.com> Signed-off-by:
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James Zhu authored
Enable vcn4 dpg mode. Signed-off-by:
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James Zhu authored
Enable JPEG PG and CG for VCN4_0_0. Reviewed-by:
Sonny Jiang <sonny.jiang@amd.com> Acked-by:
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Leo Liu authored
Most of the tiles can be power/clock gated. Reviewed-by:
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James Zhu authored
Add jpeg support for VCN4_0_0. Reviewed-by:
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Leo Liu authored
Add VCN 4.0 initialization and decoder/encoder ring functions. Signed-off-by:
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James Zhu authored
Add the interrupt source packet definitions for VCN4. Signed-off-by:
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James Zhu authored
Move out asic specific definition from common header. Acked-by:
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Leo Liu authored
Software ring will be supported only from VCN4 Signed-off-by:
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Leo Liu authored
Add VCN 4.0.0 registers Signed-off-by:
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Stanley Yang authored
Add SDMA v6 ip block for asics which support it. Signed-off-by:
Stanley Yang <Stanley.Yang@amd.com> Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
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Stanley Yang authored
Add functions for SDMA version 6. Signed-off-by:
Likun Gao <Likun.Gao@amd.com> Reviewed-by:
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Hawking Zhang authored
v1: add sdma v6_0_0 pkt definitions (Hawking) v2: add gcr control field definition (Likun) v3: correct some definitions (Likun) Signed-off-by:
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Aric Cyr authored
This version brings along following fixes: - Have optc3 function accessible to newer DCN - Add CM boot option for USB4 tunneling - Fix system hang issue when game resolution is changed - Remove outdated register for dcn3+ - Add new DSC interface to disconnect from pipe - Clean up pixel format types in enum surface_pixel_format Acked-by:
Wayne Lin <wayne.lin@amd.com> Signed-off-by:
Aric Cyr <aric.cyr@amd.com> Tested-by:
Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by:
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Anthony Koo authored
- Add new cmd for querying HPD state Reviewed-by:
Anthony Koo <Anthony.Koo@amd.com> Tested-by:
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Aric Cyr authored
[Why & How] Equate the first non-subsampled video surface format to the enum SURFACE_PIXEL_FORMAT_SUBSAMPLE_END since it's not a real format. Acked-by:
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Eric Bernstein authored
[Why & How] Add new DSC interface to disconnect from pipe. Reviewed-by:
Alvin Lee <alvin.lee2@amd.com> Acked-by:
Eric Bernstein <eric.bernstein@amd.com> Tested-by:
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Tse, Kaitlyn authored
[Why & How] Remove MPCC_OGAM_LUT_RAM_CONTROL register which is outdated. Reviewed-by:
Nevenko Stupar <Nevenko.Stupar@amd.com> Reviewed-by:
Martin Leung <Martin.Leung@amd.com> Acked-by:
Tse Kaitlyn <Kaitlyn.Tse@amd.com> Tested-by:
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Evgenii Krasnikov authored
This reverts commit d2069326. Commit d2069326 ("drm/amd/display: Reset cached PSR parameters after hibernate") causes a system hang when game resolution is changed. Revert it. Reviewed-by:
Jayendran Ramani <Jayendran.Ramani@amd.com> Reviewed-by:
Harry Vanzylldejong <Harry.Vanzylldejong@amd.com> Acked-by:
Evgenii Krasnikov <Evgenii.Krasnikov@amd.com> Tested-by:
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Jimmy Kizito authored
[Why] Boot up behaviour may differ depending on the Connection Manager handling USB4 tunneling. [How] Send boot option to firmware to indicate Connection Manager. Reviewed-by:
Jun Lei <Jun.Lei@amd.com> Acked-by:
Jimmy Kizito <Jimmy.Kizito@amd.com> Tested-by:
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Lee, Alvin authored
[Why] Newer DCN should use optc3 [How] Declare optc3 vmin/vmax function in header. Reviewed-by:
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Alex Deucher authored
Enable MES 11 on asics which support it. Signed-off-by: -
Likun Gao authored
Enable GFX 11.0 on asics where it is present. Signed-off-by:
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Jack Xiao authored
Enable KIQ to map MES ring: 1). add MES queue mapping support in MAP_QUEUES packet. 2). use correct MQD settings for MES queue. Signed-off-by:
Jack Xiao <Jack.Xiao@amd.com> Reviewed-by:
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Jack Xiao authored
Enable KIQ to map MES ring: 1). add MES queue mapping support in MAP_QUEUES packet. 2). use correct MQD settings for MES queue. Signed-off-by:
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Hawking Zhang authored
To generate an interrupt to RLC for accessing indirect registers that CP can not access directly Signed-off-by:
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Evan Quan authored
Enable Fine Grained Clock Gating on soc21 asics. Signed-off-by:
Evan Quan <evan.quan@amd.com> Signed-off-by:
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Evan Quan authored
Enable GFX CGCG (coarse grained clockgating) and CGLS (coarse grained light sleep) for GC11.0.0. Signed-off-by:
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Mukul Joshi authored
Add initial support for soc21 in KFD compute driver (Mukul) - Add new definition for soc21 device. - Add new file for amdgpu-kfd interface for GFX11 family. - Add new file for queue management, interrupt handling, mqd management for GFX11 family in KFD driver. - Related changes/updates for soc21 device in KFD driver. - Repurpose last 2 entries of SDMA MQD for driver use. v2: Add an optional argument into update queue operation (Mukul) v3: Switch to ip version check, replace kgd_dev with amdgpu_device (Hawking) Signed-off-by:Mukul Joshi <mukul.joshi@amd.com> Signed-off-by:
Oak Zeng <Oak.Zeng@amd.com> Signed-off-by:
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Alex Deucher authored
Rather than using hardcoded tables, we can use the gfx and gmc config pulled from the IP discovery table to generate the cache configuration. Acked-by:
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Hawking Zhang authored
Add initial support for GC version 11. GC is the graphics and compute block on the GPU. v1: add initial gfx11 support (Wenhui) v2: switch to new amdgpu_gfx_is_high_priority_compute_queue interface (Hawking) v3: fix num_mec (Alex) Signed-off-by:Wenhui Sheng <Wenhui.Sheng@amd.com> Reviewed-by:
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Jack Xiao authored
Initiate mes v11 code base from mes v10, rename function and register names. Signed-off-by:
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Likun Gao authored
Add support to initialize imu for gfx v11. IMU is a new power management block for gfx which manages gfx power. Signed-off-by:
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Jack Xiao authored
For mes kiq has been taken over by mes sched, drv can't directly use mes kiq to unmap queues. drv has to use mes sched api to unmap legacy queue. Signed-off-by:
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