- 18 Dec, 2023 2 commits
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Linus Walleij authored
Merge tag 'samsung-pinctrl-6.8' of https://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/samsung into devel Samsung pinctrl drivers changes for v6.8 1. New hardware: Add pin controllers for Samsung ExynosAutov920 and Google Tensor GS101. 2. Few DT bindings cleanups: add specific compatibles for each device using generic compatible as fallback. This affects only DTS, no driver changes are needed. 3. Allow setting affinity on non wake-up external GPIO interrupts. Signed-off-by:
Linus Walleij <linus.walleij@linaro.org>
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Linus Walleij authored
Merge tag 'renesas-pinctrl-for-v6.8-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel pinctrl: renesas: Updates for v6.8 (take two) - Add pinmux groups, power source, and input/output enable support for Ethernet pins on RZ/G2L SoCs, - Miscellaneous fixes and improvements. Signed-off-by:
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- 15 Dec, 2023 4 commits
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Claudiu Beznea authored
Some of the RZ/G3S Ethernet pins (P1_0, P7_0) can be configured with input enable. Enable this functionality for these pins. Signed-off-by:
Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Reviewed-by:
Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20231207070700.4156557-8-claudiu.beznea.uj@bp.renesas.comSigned-off-by:
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Claudiu Beznea authored
Some of the Ethernet pins on RZ/G3S (but also valid for RZ/G2L) need to have the direction of the IO buffer set as output for Ethernet to work properly. On RZ/G3S, these pins are P1_0/P7_0, P1_1/P7_1, and can have the following Ethernet functions: TXC/TX_CLK or TX_CTL/TX_EN. As the pins supporting output enable are SoC specific, and there is a limited number of these pins (TXC/TX_CLK and/or TX_CTL/TX_EN), specify output enable capable port limits in the platform-based configuration data structure, to ensure proper validation. The OEN support has been intantiated for RZ/G3S at the moment. Signed-off-by:
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Claudiu Beznea authored
The GPIO controller available on RZ/G3S (but also on RZ/G2L) supports setting the power source for Ethernet pins. Based on the interface b/w the Ethernet controller and the Ethernet PHY, and on board design, a specific power source needs to be selected. The GPIO controller supports 1.8V, 2.5V, and 3.3V power source selection for the Ethernet pins. This can be selected though the ETHx_POC registers (x={0, 1}). Adjust the driver to support this, and to do proper instantiation for the RZ/G3S and RZ/G2L SoCs. On RZ/G2L only the get operation has been tested at the moment. While at it, as the power registers on RZ/G2L support access sizes of 8 bits, and these registers on RZ/G3S support access sizes of 8/16/32 bits, replace writel()/readl() on these registers with writeb()/readb(). This should allow us to use the same code on both SoCs w/o any issues. Signed-off-by: -
Claudiu Beznea authored
On RZ/G3S different Ethernet pins need to be configured with different settings (e.g. power-source needs to be set, RGMII TXC and TX_CTL pins need output-enable). Adjust the driver to allow specifying pin configuration for pinmux groups. With this, DT settings like the following are taken into account by the driver: eth0_pins: eth0 { tx_ctl { pinmux = <RZG2L_PORT_PINMUX(1, 1, 1)>; /* ET0_TX_CTL */ power-source = <1800>; output-enable; drive-strength-microamp = <5200>; }; }; Signed-off-by:
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- 13 Dec, 2023 3 commits
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Claudiu Beznea authored
Move arg and index in the main block of the function as they are used by more than one case block of switch-case (3 out of 4 for arg, 2 out of 4 for index). In this way some lines of code are removed. Signed-off-by:
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Jaewon Kim authored
Add pinctrl data for ExynosAutov920 SoC. It has a newly applied pinctrl register layer for ExynosAuto series. Pinctrl data for ExynosAutoV920 SoC. - GPA0,GPA1 (10): External wake up interrupt - GPQ0 (2): SPMI (PMIC I/F) - GPB0,GPB1,GPB2,GPB3,GPB4,GPB5,GPB6 (47): I2S Audio - GPH0,GPH1,GPH2,GPH3,GPH4,GPH5,GPH6,GPH8 (49): PCIE, UFS, Ethernet - GPG0,GPG1,GPG2,GPG3,GPG4,GPG5 (29): General purpose - GPP0,GPP1,GPP2,GPP3,GPP4,GPP5,GPP6,GPP7,GPP8,GPP9,GPP10 (77): USI Signed-off-by:
Jaewon Kim <jaewon02.kim@samsung.com> Link: https://lore.kernel.org/r/20231211114145.106255-3-jaewon02.kim@samsung.comSigned-off-by:
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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Jaewon Kim authored
New ExynosAuto series GPIO have a different register structure. In the existing Exynos series, EINT control register is enumerated after a specific offset (e.g EXYNOS_GPIO_ECON_OFFSET, EXYNOS_GPIO_EMASK_OFFSET). However, from ExynosAutov920 SoC, the register that controls EINT belongs to each GPIO bank, and each GPIO bank has 0x1000 align. This is a structure to protect the GPIO bank using S2MPU in VM environment, and will only be applied in ExynosAuto series SoCs. -------------------------------------------------------------- | Original Exynos | ExynosAuto | |------------------------------------------------------------| | 0x0 GPIO_CON | 0x0 GPIO_CON | | 0x4 GPIO_DAT | 0x4 GPIO_DAT | | 0x8 GPIO_PUD | 0x8 GPIO_PUD | | 0xc GPIO_DRV | 0xc GPIO_DRV | | 0x10 GPIO_CONPDN | 0x10 GPIO_CONPDN | | 0x14 GPIO_PUDPDN | 0x14 GPIO_PUDPDN | |----------------------------| 0x18 EINT_CON (per_bank) | | ... | 0x1c EINT_FLTCON0 (per_bank) | | ... | 0x20 EINT_FLTCON1 (per_bank) | | ... | 0x24 EINT_MASK (per_bank) | | ... | 0x28 EINT_PEND (per_bank) | |----------------------------|-------------------------------| | 0x700 EINT_CON (global) | ... | | 0x800 EINT_FLTCON (global) | ... | | 0x900 EINT_MASK (global) | ... | | 0xa00 EINT_FEND (global) | ... | -------------------------------------------------------------- Signed-off-by:
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- 12 Dec, 2023 7 commits
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Linus Walleij authored
Immutable tag for the PEF2256 framer
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Herve Codina authored
After contributing the driver, add myself as the maintainer for the Lantiq PEF2256 driver. Signed-off-by:
Herve Codina <herve.codina@bootlin.com> Reviewed-by:
Christophe Leroy <christophe.leroy@csgroup.eu> Link: https://lore.kernel.org/r/20231128132534.258459-6-herve.codina@bootlin.comSigned-off-by:
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Herve Codina authored
The Lantiq PEF2256 is a framer and line interface component designed to fulfill all required interfacing between an analog E1/T1/J1 line and the digital PCM system highway/H.100 bus. This kind of component can be found in old telecommunication system. It was used to digital transmission of many simultaneous telephone calls by time-division multiplexing. Also using HDLC protocol, WAN networks can be reached through the framer. This pinmux support handles the pin muxing part (pins RP(A..D) and pins XP(A..D)) of the PEF2256. Signed-off-by:
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Herve Codina authored
The Lantiq PEF2256 is a framer and line interface component designed to fulfill all required interfacing between an analog E1/T1/J1 line and the digital PCM system highway/H.100 bus. Signed-off-by:
Jakub Kicinski <kuba@kernel.org> Link: https://lore.kernel.org/r/20231128132534.258459-4-herve.codina@bootlin.comSigned-off-by:
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Herve Codina authored
The Lantiq PEF2256 is a framer and line interface component designed to fulfill all required interfacing between an analog E1/T1/J1 line and the digital PCM system highway/H.100 bus. Signed-off-by:
Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20231128132534.258459-3-herve.codina@bootlin.comSigned-off-by:
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Herve Codina authored
A framer is a component in charge of an E1/T1 line interface. Connected usually to a TDM bus, it converts TDM frames to/from E1/T1 frames. It also provides information related to the E1/T1 line. The framer framework provides a set of APIs for the framer drivers (framer provider) to create/destroy a framer and APIs for the framer users (framer consumer) to obtain a reference to the framer, and use the framer. This basic implementation provides a framer abstraction for: - power on/off the framer - get the framer status (line state) - be notified on framer status changes - get/set the framer configuration Signed-off-by:
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Peter Griffin authored
Add support for the pin-controller found on the gs101 SoC used in Pixel 6 phones. Reviewed-by:
Sam Protsenko <semen.protsenko@linaro.org> Signed-off-by:
Peter Griffin <peter.griffin@linaro.org> Acked-by:
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- 11 Dec, 2023 15 commits
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Andy Shevchenko authored
All drivers are converted to use embedded struct pingroup. Remove unused members from struct group_desc. Reviewed-by:
Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20231211190321.307330-14-andriy.shevchenko@linux.intel.comSigned-off-by:
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Andy Shevchenko authored
Convert drivers to use grp member embedded in struct group_desc, because other members will be removed to avoid duplication and desynchronisation of the generic pin group description. Reviewed-by:
Emil Renner Berthing <emil.renner.berthing@canonical.com> Signed-off-by:
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Andy Shevchenko authored
Convert drivers to use grp member embedded in struct group_desc, because other members will be removed to avoid duplication and desynchronisation of the generic pin group description. Reviewed-by:
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Andy Shevchenko authored
Convert drivers to use grp member embedded in struct group_desc, because other members will be removed to avoid duplication and desynchronisation of the generic pin group description. Signed-off-by:
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Andy Shevchenko authored
Convert drivers to use grp member embedded in struct group_desc, because other members will be removed to avoid duplication and desynchronisation of the generic pin group description. Signed-off-by:
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Andy Shevchenko authored
Convert drivers to use grp member embedded in struct group_desc, because other members will be removed to avoid duplication and desynchronisation of the generic pin group description. Acked-by:
Paul Cercueil <paul@crapouillou.net> Signed-off-by:
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Andy Shevchenko authored
Convert drivers to use grp member embedded in struct group_desc, because other members will be removed to avoid duplication and desynchronisation of the generic pin group description. Signed-off-by:
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Andy Shevchenko authored
Convert drivers to use grp member embedded in struct group_desc, because other members will be removed to avoid duplication and desynchronisation of the generic pin group description. Signed-off-by:
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Andy Shevchenko authored
Convert drivers to use grp member embedded in struct group_desc, because other members will be removed to avoid duplication and desynchronisation of the generic pin group description. Tested-by:
Florian Fainelli <florian.fainelli@broadcom.com> Reviewed-by:
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Andy Shevchenko authored
struct group_desc is a particular version of the struct pingroup with associated opaque data. Start switching pin control core and drivers to use it explicitly. Reviewed-by:
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Andy Shevchenko authored
For the better flexibility use C99 initializers in PINCTRL_PIN_GROUP(). Signed-off-by:
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Andy Shevchenko authored
For the better flexibility use C99 initializers in PINCTRL_PIN_GROUP(). Signed-off-by:
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Andy Shevchenko authored
Add PINCTRL_GROUP_DESC() macro for inline use. Reviewed-by:
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Linus Walleij authored
Merge tag 'gpio-remove-gpiochip_is_requested-for-v6.8-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/brgl/linux into devel gpio: remove gpiochip_is_requested() - provide a safer alternative to gpiochip_is_requested() - convert all existing users - remove gpiochip_is_requested()
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Krzysztof Kozlowski authored
ExynosAutov920 SoC wake-up pin controller has different register layout than Exynos7, thus it should not be marked as compatible. Neither DTS nor Linux driver was merged yet, so the change does not impact ABI. Cc: Jaewon Kim <jaewon02.kim@samsung.com> Fixes: 904140fa ("dt-bindings: pinctrl: samsung: use Exynos7 fallbacks for newer wake-up controllers") Link: https://lore.kernel.org/r/20231210133915.42112-1-krzysztof.kozlowski@linaro.orgReviewed-by:
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- 10 Dec, 2023 2 commits
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Peter Griffin authored
gs101 is similar to newer Exynos SoCs like Exynos850 and ExynosAutov9 where more than one pin controller can do external wake-up interrupt. So add a dedicated compatible for it. Reviewed-by:
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Peter Griffin authored
Add the "google,gs101-pinctrl" compatible to the dt-schema bindings documentation. Reviewed-by:
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- 08 Dec, 2023 7 commits
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Bartosz Golaszewski authored
We have no external users of gpiochip_is_requested(). Let's remove it and replace its internal calls with direct testing of the REQUESTED flag. Signed-off-by:
Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Acked-by:
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Bartosz Golaszewski authored
Rework for_each_requested_gpio_in_range() to use the new helper to retrieve a dynamically allocated copy of the descriptor label and free it at the end of each iteration. We need to leverage the CLASS()' destructor to make sure that the label is freed even when breaking out of the loop. Signed-off-by:
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Bartosz Golaszewski authored
Use the new gpiochip_dup_line_label() helper to safely retrieve the descriptor label. Signed-off-by:
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Bartosz Golaszewski authored
Use the new gpiochip_dup_line_label() helper to safely retrieve the descriptor label. Signed-off-by:
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Bartosz Golaszewski authored
Use the new gpiochip_dup_line_label() helper to safely retrieve the descriptor label. Signed-off-by:
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Bartosz Golaszewski authored
Use the new gpiochip_dup_line_label() helper to safely retrieve the descriptor label. Signed-off-by:
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Bartosz Golaszewski authored
Use the new gpiochip_dup_line_label() helper to safely retrieve the descriptor label. Signed-off-by:
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