- 10 Nov, 2017 1 commit
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Arnd Bergmann authored
The driver fails to build without CONFIG_OF: drivers/pinctrl/samsung/pinctrl-samsung.c: In function 'samsung_gpiolib_register': drivers/pinctrl/samsung/pinctrl-samsung.c:936:5: error: 'struct gpio_chip' has no member named 'of_node' This configuration is now possible since we can now select the PINCTRL subsystem on S3C24xx machines other than the device tree based ones. Fixes: d219b924 ("pinctrl: change Kconfig PINCTRL variable to a menuconfig") Signed-off-by:
Arnd Bergmann <arnd@arndb.de> Signed-off-by:
Linus Walleij <linus.walleij@linaro.org>
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- 09 Nov, 2017 2 commits
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Linus Walleij authored
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Linus Walleij authored
Fixing a small merge problem in BCM2835 related to the new irqchip code. Cc: Thierry Reding <treding@nvidia.com> Signed-off-by:
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- 08 Nov, 2017 23 commits
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Linus Walleij authored
The struct is wrong, this is named lock_class_key. Cc: Thierry Reding <treding@nvidia.com> Signed-off-by: -
Thierry Reding authored
In order to avoid lockdep boilerplate in individual drivers, turn the gpiochip_add_data() function into a macro that creates a unique class key for each driver. Note that this has the slight disadvantage of adding a key for each driver registered with the system. However, these keys are 8 bytes in size, which is negligible and a small price to pay for generic infrastructure. Suggested-by:
Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by:
Thierry Reding <treding@nvidia.com> Acked-by:
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Thierry Reding authored
Some GPIO chips cannot support sparse IRQ numbering and therefore need to manually allocate their interrupt descriptors statically. For these cases, a driver can pass the first allocated IRQ via the struct gpio_irq_chip's "first" field and thereby cause the IRQ domain to map all IRQs during initialization. Suggested-by:
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Thierry Reding authored
The nested field in struct gpio_irq_chip currently has two meanings. On one hand it marks an IRQ chip as being nested (as opposed to chained), while on the other hand it also means that an IRQ chip uses nested thread handlers. However, nested IRQ chips can already be identified by the fact that they don't pass a parent handler (the driver would instead already have installed a nested handler using request_irq()). Therefore, the only use for the nested attribute is to inform gpiolib that an IRQ chip uses nested thread handlers (as opposed to regular, non-threaded handlers). To clarify its purpose, rename the field to "threaded". Signed-off-by:
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Thierry Reding authored
Tegra186 has two GPIO controllers that are largely register compatible between one another but are completely different from the controller found on earlier generations. Signed-off-by:
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Thierry Reding authored
Export these functions so that drivers can explicitly use these when setting up their IRQ domain. Signed-off-by:
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Thierry Reding authored
Currently GPIO drivers are required to add the GPIO chip and its corresponding IRQ chip separately, which can result in a lot of boilerplate. Use the newly introduced struct gpio_irq_chip, embedded in struct gpio_chip, that drivers can fill in if they want the GPIO core to automatically register the IRQ chip associated with a GPIO chip. Signed-off-by:
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Thierry Reding authored
In order to consolidate the multiple ways to associate an IRQ chip with a GPIO chip, move more fields into the new struct gpio_irq_chip. Signed-off-by:
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Thierry Reding authored
In order to consolidate the multiple ways to associate an IRQ chip with a GPIO chip, move more fields into the new struct gpio_irq_chip. Signed-off-by:
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Thierry Reding authored
In order to consolidate the multiple ways to associate an IRQ chip with a GPIO chip, move more fields into the new struct gpio_irq_chip. Signed-off-by:
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Thierry Reding authored
In order to consolidate the multiple ways to associate an IRQ chip with a GPIO chip, move more fields into the new struct gpio_irq_chip. Signed-off-by:
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Thierry Reding authored
In order to consolidate the multiple ways to associate an IRQ chip with a GPIO chip, move more fields into the new struct gpio_irq_chip. Signed-off-by:
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Thierry Reding authored
In order to consolidate the multiple ways to associate an IRQ chip with a GPIO chip, move more fields into the new struct gpio_irq_chip. Signed-off-by:
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Thierry Reding authored
In order to consolidate the multiple ways to associate an IRQ chip with a GPIO chip, move more fields into the new struct gpio_irq_chip. Signed-off-by:
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Thierry Reding authored
In order to consolidate the multiple ways to associate an IRQ chip with a GPIO chip, move more fields into the new struct gpio_irq_chip. Signed-off-by:
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Thierry Reding authored
This new structure will be used to group all fields related to interrupt handling in a GPIO chip. Doing so will properly namespace these fields and make it easier to distinguish which fields are used for IRQ support. Signed-off-by:
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Linus Walleij authored
The GMII groups need to be split across GMAC0 and GMAC1 since GMAC0 is always available but GMAC1 masks GPIO2 lines 0-7 so we might want just one interface out. Signed-off-by: -
Rajendra Nayak authored
Update the binding and driver for pmi8994-gpios Signed-off-by:
Rajendra Nayak <rnayak@codeaurora.org> Signed-off-by:
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Colin Ian King authored
The pointer dev is being assigned but is never used, hence it is redundant and can be removed. Cleans up clang warnings: drivers/pinctrl/ti/pinctrl-ti-iodelay.c:582:2: warning: Value stored to 'dev' is never read drivers/pinctrl/ti/pinctrl-ti-iodelay.c:701:2: warning: Value stored to 'dev' is never read Signed-off-by:
Colin Ian King <colin.king@canonical.com> Signed-off-by:
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Markus Elfring authored
* Add a jump target so that a specific error message is stored only once at the end of this function implementation. * Replace two calls of the function "dev_err" by goto statements. * Adjust two condition checks. This issue was detected by using the Coccinelle software. Signed-off-by:
Markus Elfring <elfring@users.sourceforge.net> Signed-off-by:
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Linus Walleij authored
This enabled pin config on the Gemini driver and implements pin skew/delay so that the ethernet pins clocking can be properly configured. Acked-by:
Hans Ulli Kroll <ulli.kroll@googlemail.com> Signed-off-by:
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Linus Walleij authored
We can just use the generic Device Tree parser code in this driver and save some code. Acked-by:
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Linus Walleij authored
Some pin controllers (such as the Gemini) can control the expected clock skew and output delay on certain pins with a sub-nanosecond granularity. This is typically done by shunting in a number of double inverters in front of or behind the pin. Make it possible to configure this with a generic binding. Cc: devicetree@vger.kernel.org Acked-by:
Rob Herring <robh@kernel.org> Acked-by:
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- 03 Nov, 2017 1 commit
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Arnd Bergmann authored
A cleanup left behind a temporary variable that is now unused: drivers/pinctrl/mvebu/pinctrl-armada-37xx.c: In function 'armada_37xx_irq_startup': drivers/pinctrl/mvebu/pinctrl-armada-37xx.c:693:20: error: unused variable 'chip' [-Werror=unused-variable] This removes the declarations as well. Fixes: 3ee9e605 ("pinctrl: armada-37xx: Stop using struct gpio_chip.irq_base") Signed-off-by:
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- 31 Oct, 2017 13 commits
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Ard Biesheuvel authored
Commit fd9c963c ("gpio: mb86s70: Return error if requesting an already assigned gpio") adds code that infers from the state of the GPIO Pin Function Register (PFR) whether a GPIO has been assigned already. This assumes that the pin functions are set to 'peripheral' when the driver is loaded, which is not guaranteed. Also, the GPIO layer is perfectly capable of keeping track of which GPIOs have been assigned already, so we shouldn't need this check in the first place. This reverts commit fd9c963c. Cc: Axel Lin <axel.lin@ingics.com> Signed-off-by:
Ard Biesheuvel <ard.biesheuvel@linaro.org> Acked-by:
Axel Lin <axel.lin@ingics.com> Signed-off-by:
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Ard Biesheuvel authored
In order to reuse this driver for the Socionext Synquacer SC2A11 SoC, which inherited this IP from Fujitsu, remove the ARCH_MB86S7X Kconfig dependency, and revert the changes that prevent it from being built as a module. This reverts commits d65aa4b6 and d5610e51. Cc: Geliang Tang <geliangtang@gmail.com> Cc: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by:
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Ken Ma authored
Current edge both type gpio irqs which need to swap polarity in each interrupt are not supported, this patch adds edge both type gpio irq support. Signed-off-by:
Ken Ma <make@marvell.com> Signed-off-by:
Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by:
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Doug Berger authored
This commit corrects problems with the previous wake implementation by implementing suspend and resume power management operations and the driver shutdown operation. Wake masks are used to keep track of which GPIO should wake the device. On suspend the GPIO state is saved and the possible wakeup sources are explicitly unmasked in the hardware. Non-wakeup sources are explicitly masked so IRQCHIP_MASK_ON_SUSPEND is no longer necessary. The saved state of the GPIO is restored upon resume. It is important not to write to the GPIO status register since this has the effect of clearing bits. The status register is explicitly removed from the register save and restore to ensure this. The shutdown operation allows the hardware to be put into the same quiesced state as the suspend operation and removes the need for the reboot notifier. Unfortunately, there appears to be some confusion about whether a pending disabled wake interrupt should wake the system. If a wake capable interrupt is disabled using the default "lazy disable" behavior and it is triggered before the suspend_device_irq call the interrupt hardware will be acknowledged by mask_ack_irq and the IRQS_PENDING flag is added to its state. However, the IRQS_PENDING flag of wake interrupts is not checked to prevent the transition to suspend and the hardware has been acked which prevents its wakeup. If the lazy disabled interrupt is triggered after the call to suspend_device_irqs then the wakeup logic will abort the suspend. The irq_disable method is defined by this GPIO driver to prevent lazy disable so that the pending hardware state remains asserted allowing the hardware to wake and providing a consistent behavior. In addition, the IRQ_DISABLE_UNLAZY flag is set for the non-wake parent interrupt as a convenience to prevent the need to add code to the brcmstb_gpio_irq_handler to support "lazy disable" of the non-wake parent interrupt when it is disabled during suspend and resume. Chained interrupt parents are not normally disabled, but these GPIO devices have different parent interrupts for wake and non-wake handling. It is convenient to mask the non-wake parent when suspending to preserve the hardware state for proper wakeup accounting when the driver is resumed. Signed-off-by:
Doug Berger <opendmb@gmail.com> Acked-by:
Gregory Fong <gregory.0xf0@gmail.com> Reviewed-by:
Florian Fainelli <f.fainelli@gmail.com> Signed-off-by:
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Doug Berger authored
The GPIOLIB IRQ chip helpers were very appealing, but badly broke the 1:1 mapping between a GPIO controller's device_node and its interrupt domain. When another device-tree node references a GPIO device as its interrupt parent, the irq_create_of_mapping() function looks for the irq domain of the GPIO device and since all bank irq domains reference the same GPIO device node it always resolves to the irq domain of the first bank regardless of which bank the number of the GPIO should resolve. This domain can only map hwirq numbers 0-31 so interrupts on GPIO above that can't be mapped by the device-tree. This commit effectively reverts the patch from Gregory Fong [1] that was accepted upstream and replaces it with a consolidated irq domain implementation with one larger interrupt domain per GPIO controller instance spanning multiple GPIO banks based on an earlier patch [2] also submitted by Gregory Fong. [1] https://patchwork.kernel.org/patch/6921561/ [2] https://patchwork.kernel.org/patch/6347811/ Fixes: 19a7b694 ("gpio: brcmstb: Add interrupt and wakeup source support") Signed-off-by:
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Doug Berger authored
This commit corrects a bug when configuring the GPIO hardware for IRQ_TYPE_LEVEL_LOW and IRQ_TYPE_LEVEL_HIGH interrupt types. The hardware is now correctly configured to support those types. Fixes: 19a7b694 ("gpio: brcmstb: Add interrupt and wakeup source support") Signed-off-by:
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Doug Berger authored
Reading and writing the gpio bank status register each time a pending interrupt bit is serviced could cause new pending bits to be cleared without servicing the associated interrupts. By using the handle_level_irq flow instead of the handle_simple_irq flow we get proper handling of interrupt masking as well as acking of interrupts. The irq_ack method is added to support this. Fixes: 19a7b694 ("gpio: brcmstb: Add interrupt and wakeup source support") Signed-off-by:
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Doug Berger authored
The basic memory-mapped GPIO controller lock must be released before calling the registered GPIO interrupt handlers to allow the interrupt handlers to access the hardware. Examples of why a GPIO interrupt handler might want to access the GPIO hardware include an interrupt that is configured to trigger on rising and falling edges that needs to read the current level of the input to know how to respond, or an interrupt that causes a change in a GPIO output in the same bank. If the lock is not released before enterring the handler the hardware accesses will deadlock when they attempt to grab the lock. Since the lock is only needed to protect the calculation of unmasked pending interrupts create a dedicated function to perform this and hide the complexity. Fixes: 19a7b694 ("gpio: brcmstb: Add interrupt and wakeup source support") Signed-off-by:
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Doug Berger authored
This commit allows a wakeup parent interrupt to be shared between instances. It also removes the redundant can_wake member of the private data structure by using whether the parent_wake_irq has been defined to indicate that the GPIO device can wake. Fixes: 19a7b694 ("gpio: brcmstb: Add interrupt and wakeup source support") Signed-off-by:
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Masahiro Yamada authored
This is handled by the mmc-pwrseq-emmc driver, which controls an eMMC hardware reset via a GPIO line. Remove it from the function pin-mux settings. Signed-off-by:
Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by:
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Heiko Stuebner authored
The rk3288 also has one function that can be routed to one of two pins, the hdmi cec functionality can use either gpio7c0 or gpio7c7. So add the route switching support for it. Signed-off-by:
Heiko Stuebner <heiko@sntech.de> Tested-by:
Hans Verkuil <hans.verkuil@cisco.com> Reviewed-by:
David Wu <david.wu@rock-chips.com> Signed-off-by:
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Mika Westerberg authored
Intel Cedar Fork PCH is the successor of Intel Denverton PCH but it is based on the newer GPIO/pinctrl hardware block. Add a new pinctrl/GPIO driver to support it. Signed-off-by:
Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by:
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Mika Westerberg authored
Some GPIO blocks have the interrupt status (GPI_IS) offset different than it normally is, so make it configurable. If no offset is specified we use the default. While there remove two unused constants from the core driver. Signed-off-by:
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