- 12 Mar, 2021 40 commits
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Bjorn Andersson authored
Add initial DTS for the Snapdragon 888 Mobile Hardware Development Kit, aka SM8350 HDK. This initial version describes debug UART, UFS storage, the three USB connectors and remoteprocs. Reviewed-by:
Konrad Dybcio <konrad.dybcio@somainline.org> Reviewed-by:
Vinod Koul <vkoul@kernel.org> Signed-off-by:
Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210308182113.1284966-1-bjorn.andersson@linaro.orgSigned-off-by:
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Vinod Koul authored
Document the various sony boards for apq8094. These are used in various sony dts files but not documented Signed-off-by:
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Vinod Koul authored
We expect bootloader to full memory details but passing empty values gives warning, so add a default value arch/arm64/boot/dts/qcom/apq8094-sony-xperia-kitakami-karin_windy.dt.yaml: /: memory: False schema does not allow {'device_type': ['memory'], 'reg': [[0, 0, 0, 0]]} Signed-off-by: -
Vinod Koul authored
Document the ipq6018-cp01 board. It was missing leading to warning: arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dt.yaml: /: compatible: 'oneOf' conditional failed, one must be fixed: ['qcom,ipq6018-cp01', 'qcom,ipq6018'] is too short ['qcom,ipq6018-cp01', 'qcom,ipq6018'] is too long Additional items are not allowed ('qcom,ipq6018' was unexpected) Signed-off-by: -
Vinod Koul authored
We expect bootloader to full memory details but passing empty values gives warning, so add a default value arch/arm64/boot/dts/qcom/apq8016-sbc.dt.yaml: /: memory: False schema does not allow {'device_type': ['memory'], 'reg': [[0, 0, 0, 0]]} Signed-off-by: -
Vinod Koul authored
apq8016-sbc is one of the compaitibles for this board, but is not documented, so drop it. This fixes these two warns: arch/arm64/boot/dts/qcom/apq8016-sbc.dt.yaml: /: compatible: ['qcom,apq8016-sbc', 'qcom,apq8016', 'qcom,sbc'] is not valid under any of the given schemas (Possible causes of the failure): arch/arm64/boot/dts/qcom/apq8016-sbc.dt.yaml: /: compatible: ['qcom,apq8016-sbc', 'qcom,apq8016', 'qcom,sbc'] is too long arch/arm64/boot/dts/qcom/apq8016-sbc.dt.yaml: /: compatible:0: 'qcom,apq8016-sbc' is not one of ['qcom,apq8064-cm-qs600', 'qcom,apq8064-ifc6410'] arch/arm64/boot/dts/qcom/apq8016-sbc.dt.yaml: /: compatible:0: 'qcom,apq8016-sbc' is not one of ['qcom,apq8074-dragonboard'] Signed-off-by:
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Douglas Anderson authored
At boot time the following happens: 1. Device core gets ready to probe our SPI driver. 2. Device core applies SPI controller's "default" pinctrl. 3. Device core calls the SPI driver's probe() function which will eventually setup the chip select GPIO as "unasserted". Thinking about the above, we can find: a) For SPI devices that the BIOS inits (Cr50 and EC), the BIOS would have had them configured as "GENI" pins and not as "GPIO" pins. b) It turns out that our BIOS also happens to init these pins as "output" (even though it doesn't need to since they're not muxed as GPIO) but leaves them at the default state of "low". c) As soon as we apply the "default" chip select it'll switch the function to GPIO and stop driving the chip select high (which is how "GENI" was driving it) and start driving it low. d) As of commit 9378f46040be ("UPSTREAM: spi: spi-geni-qcom: Use the new method of gpio CS control"), when the SPI core inits things it inits the GPIO to be "deasserted". Prior to that commit the GPIO was left untouched until first use. e) When the first transaction happens we'll assert the chip select and then deassert it after done. So before the commit to change us to use gpio descriptors we used to have a _really long_ assertion of chip select before our first transaction (because it got pulled down and then the first "assert" was a no-op). That wasn't great but (apparently) didn't cause any real harm. After the commit to change us to use gpio descriptors we end up glitching the chip select line during probe. It would go low and then high with no data transferred. The other side ought to be robust against this, but it certainly could cause some confusion. It's known to at least cause an error message on the EC console and it's believed that, under certain timing conditions, it could be getting the EC into a confused state causing the EC driver to fail to probe. Let's fix things to avoid the glitch. We'll add an extra pinctrl entry that sets the value of the pin to output high (CS deasserted) before doing anything else. We'll do this in its own pinctrl node that comes before the normal pinctrl entries to ensure that the order is correct and that this gets applied before the mux change. This change is in the trogdor board file rather than in the SoC dtsi file because chip select polarity can be different depending on what's hooked up and it doesn't feel worth it to spam the SoC dtsi file with both options. The board file would need to pick the right one anyway. Reviewed-by:Stephen Boyd <swboyd@chromium.org> Fixes: cfbb97fd ("arm64: dts: qcom: Switch sc7180-trogdor to control SPI CS via GPIO") Signed-off-by:
Douglas Anderson <dianders@chromium.org> Link: https://lore.kernel.org/r/20210218145456.1.I1da01a075dd86e005152f993b2d5d82dd9686238@changeidSigned-off-by:
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Sandeep Maheswaram authored
Using pdc interrupts for USB instead of GIC interrupts to support wake up in case xo shutdown. Reviewed-by:
Sandeep Maheswaram <sanm@codeaurora.org> Link: https://lore.kernel.org/r/1594235417-23066-4-git-send-email-sanm@codeaurora.orgSigned-off-by:
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Douglas Anderson authored
This is a trogdor variant. This is mostly a grab from the downstream tree with notable exceptions: - I skip -rev0. This was a super early build and there's no advantage of long term support. - I remove sound node since sound hasn't landed upstream yet. Cc: Gwendal Grignou <gwendal@chromium.org> Cc: Matthias Kaehlcke <mka@chromium.org> Cc: Stephen Boyd <swboyd@chromium.org> Cc: Tzung-Bi Shih <tzungbi@chromium.org> Cc: Judy Hsiao <judyhsiao@chromium.org> Signed-off-by:
Matthias Kaehlcke <mka@chromium.org> Reviewed-by:
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Douglas Anderson authored
This is a trogdor variant. This is mostly a grab from the downstream tree with notable exceptions: - I skip -rev0. This was a super early build and there's no advantage of long term support. - In -rev1 I translate the handling of the USB hub like is done for similar boards. See the difference between the downstream and upstream 'sc7180-trogdor-lazor-r0.dts' for an example. This will need to be resolved when proper support for the USB hub is figured out upstream. - I remove sound node since sound hasn't landed upstream yet. - In incorporate the pending <https://crrev.com/c/2719075> for the keyboard. Cc: Philip Chen <philipchen@google.com> Cc: Matthias Kaehlcke <mka@chromium.org> Cc: Stephen Boyd <swboyd@chromium.org> Cc: Tzung-Bi Shih <tzungbi@chromium.org> Cc: Judy Hsiao <judyhsiao@chromium.org> Signed-off-by:
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Douglas Anderson authored
This is a SKU variant of lazor. Add it. This squashes the downstream patches to support this hardware. NOTES: - The non-touch SKU actually has "innolux,n116bca-ea1" but that driver is still pending in simple-panel. The bindings have been Acked though [1]. Things work well enough with the "innolux,n116bge" timings for now, though. - The wonky special dts just for "-rev4" arguably doesn't need to go upstream since they weren't widely distributed, but since a few people have them we might as well. If it ever causes problems we can delete it. [1] https://lore.kernel.org/r/20210115144345.v2.4.I6889e21811df6adaff5c5b8a8c80fda0669ab3a5@changeid Cc: Stephen Boyd <swboyd@chromium.org> Signed-off-by:
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Matthias Kaehlcke authored
Lazor rev3 and later use the 'lite' version of the SC7180 SoC. Reviewed-by:
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Abhishek Kumar authored
For trogdor, in the latest board-2.bin file, new BDF with variant name GO_LAZOR has been introduced, so we need this property set, for GO_LAZOR BDF to be picked. Cc: Philip Chen <philipchen@chromium.org> Signed-off-by:
Abhishek Kumar <kuabhs@chromium.org> [dianders: adjusted subject line and sort order] Signed-off-by:
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Venkata Lakshmi Narayana Gubba authored
Removed voting for RPMH_RF_CLK2 which is not required as it is getting managed by BT SoC through SW_CTRL line. Cc: Matthias Kaehlcke <mka@chromium.org> Signed-off-by:
Venkata Lakshmi Narayana Gubba <gubbaven@codeaurora.org> Signed-off-by:
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Alexandru M Stan authored
Removed the pinctrl and pin{mux,conf} for the control pins because: 1. The only need for them is for userspace control via flash_fp_mcu 2. cros-ec doesn't know what to do with them, and even if it did, it would interfere with flash_fp_mcu at the most inopportune times Since we're not using hogs, we rely on AP firmware to set all the control pins correctly. Reviewed-by:Alexandru M Stan <amstan@chromium.org> [dianders: adjusted since coachz isn't upstream yet] Reviewed-by; Matthias Kaehlcke <mka@chromium.org> Signed-off-by:
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Stephen Boyd authored
We only want to use this clk driver on CoachZ devices. Disable it for all other Trogdor boards. NOTE: CoachZ devices aren't yet supported upstream so until it is this is just disabled for all trogdor. Cc: Tomasz Figa <tfiga@chromium.org> Signed-off-by:
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Stephen Boyd authored
Configure the pen to be a wakeup source only when the pen is ejected instead of both when the pen is ejected and inserted. This corresponds to wake source requirements. Signed-off-by:
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Douglas Anderson authored
Let's avoid a bit of duplication by pushing this up to the trogdor.dtsi file. Suggested-by:
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Douglas Anderson authored
The trackpad interrupt got renamed and also moved to a new GPIO on newer boards. Let's do the move in the "trogdor.dtsi" file and then undo it in the two old boards. NOTE: since none of the new boards have device trees yet, this change looks silly on its own but it will make sense after more boards are supported. Signed-off-by:
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Douglas Anderson authored
In general pinconf belongs in board files, not SoC files. Move it to the only current user (trogdor). Also adjust the drive strengths and pulls. Cc: V Sujith Kumar Reddy <vsujithk@codeaurora.org> Cc: Srinivasa Rao Mandadapu <srivasam@codeaurora.org> Cc: Tzung-Bi Shih <tzungbi@chromium.org> Cc: Judy Hsiao <judyhsiao@chromium.org> Signed-off-by:
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Stephen Boyd authored
Drop the old node and add the new one in its place. Cc: Stephen Boyd <swboyd@chromium.org> Cc: Jeykumar Sankaran <jsanka@codeaurora.org> Cc: Chandan Uddaraju <chandanu@codeaurora.org> Cc: Vara Reddy <varar@codeaurora.org> Cc: Tanmay Shah <tanmay@codeaurora.org> Cc: Rob Clark <robdclark@chromium.org> Signed-off-by:
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Vinod Koul authored
Add cpufreq node and reference it for the CPUs. Signed-off-by:
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Vinod Koul authored
Now that we have GCC define, use the enums instead of numbers in the DTS Signed-off-by:
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Vinod Koul authored
This enabled the four remoteprocs found in SM8350, audio, compute, modem and sensor for MTP platform and adds firmware for them. Signed-off-by:
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Vinod Koul authored
Add remoteproc nodes for the audio, compute and sensor cores, define glink for each one. Signed-off-by:
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Vinod Koul authored
SMP2P is used for interrupting and being interrupted about remoteproc state changes related to the audio, compute, modem and sensor subsystems. Signed-off-by:
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Vinod Koul authored
Add the rmtfs as a reserved memory node. Signed-off-by:
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Vinod Koul authored
This adds RPMH power domain found in SM8350 SoC Signed-off-by:
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Vinod Koul authored
Fix the typo s/Limaited/Limited Signed-off-by:
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Vinod Koul authored
Add the property "regulator-names" to the regulators as given in schematics so that it is easier to understand the regulators being used Signed-off-by:
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Vinod Koul authored
Enabled the UFS node found in SM8350-MTP platform, also add the regulators associated with UFS HC and UFS phy to these nodes. Signed-off-by:
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Vinod Koul authored
This adds UFS HC and UFS phy nodes to the SM8350 DTS Signed-off-by:
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Jack Pham authored
Enable both USB controllers and associated hsphy and qmp phy nodes on sm8350 MTP. Designate the usb_1 instance as peripheral-mode only until proper PMIC based Type-C dual-role handling is supported. TODO: the second USB controller is exposed to a microAB port. Dual- role can be supported for this by adding the "usb-role-switch" property as well as defining a USB connector node with a "gpio-usb-b-connector" compatible. However, this requires GPIO support from PM8350 which is still missing. Signed-off-by:
Jack Pham <jackp@codeaurora.org> Link: https://lore.kernel.org/r/20210116013802.1609-3-jackp@codeaurora.orgSigned-off-by:
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Jack Pham authored
Add device nodes for the two instances each of USB3 controllers, QMP SS PHYs and SNPS HS PHYs. Signed-off-by:
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Vinod Koul authored
This adds apss_smmu node to SM8350 DTS Signed-off-by:
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Sai Prakash Ranjan authored
ARM architected timer interrupts DT property specifies EL2/HYP physical interrupt and not EL2/HYP virtual interrupt for the 4th interrupt property. As per interrupt documentation for SM8250 SoC, the EL2/HYP physical timer interrupt is 10 and EL2/HYP virtual timer interrupt is 12, so fix the 4th timer interrupt to be EL2 physical timer interrupt (10 in this case). Fixes: 60378f1a ("arm64: dts: qcom: sm8250: Add sm8250 dts file") Signed-off-by:
Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org> Link: https://lore.kernel.org/r/744e58f725d279eb2b049a7da42b0f09189f4054.1613468366.git.saiprakash.ranjan@codeaurora.orgSigned-off-by:
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Sai Prakash Ranjan authored
As per interrupt documentation for SM8350 SoC, the polarity for level triggered PMU interrupt is low, fix this. Fixes: b7e8f433 ("arm64: dts: qcom: Add basic devicetree support for SM8350 SoC") Signed-off-by:
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Sai Prakash Ranjan authored
As per interrupt documentation for SM8250 SoC, the polarity for level triggered PMU interrupt is low, fix this. Fixes: 60378f1a ("arm64: dts: qcom: sm8250: Add sm8250 dts file") Signed-off-by:
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Sai Prakash Ranjan authored
Use the generic DT node name "power-controller" for AOSS message ram instead of the protocol name QMP(Qualcomm Messaging Protocol) since it is used for power management requests. Reviewed-by:
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Sai Prakash Ranjan authored
Use the generic DT node name "power-controller" for AOSS message ram instead of the protocol name QMP(Qualcomm Messaging Protocol) since it is used for power management requests. Reviewed-by:
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