- 28 Jun, 2022 6 commits
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Dmitry Baryshkov authored
According to the downstram DT file, the qusb2phy ref clock should be GCC_RX0_USB2_CLKREF_CLK, not GCC_RX1_USB2_CLKREF_CLK. Fixes: c65a4ed2 ("arm64: dts: qcom: sdm630: Add USB configuration") Cc: Konrad Dybcio <konrad.dybcio@somainline.org> Reviewed-by:
Konrad Dybcio <konrad.dybcio@somainline.org> Reviewed-by:
Marijn Suijten <marijn.suijten@somainline.org> Signed-off-by:
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by:
Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220521202708.1509308-5-dmitry.baryshkov@linaro.org
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Dmitry Baryshkov authored
The SoC's device tree file disables gpucc and adreno's SMMU by default. So let's disable the GPU too. Moreover it looks like SMMU might be not usable without additional patches (which means that GPU is unusable too). No board uses GPU at this moment. Fixes: 5cf69dcb ("arm64: dts: qcom: sdm630: Add Adreno 508 GPU configuration") Reviewed-by:
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Dmitry Baryshkov authored
Follow the typical practice and keep DSI1/DSI1 PHY disabled by default. They should be enabled in the board DT files. No existing boards use them at this moment. Reviewed-by:
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Dmitry Baryshkov authored
Follow the typical practice and keep DSI0/DSI0 PHY disabled by default. They should be enabled in the board DT files. No existing boards use them at this moment. Suggested-by:
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Krzysztof Kozlowski authored
The PM8916 and PMS405 PMIC GPIOs are interrupt controllers, as described in the bindings and used by the driver. Drop the interrupts (apparently copied from downstream tree), just like in commit 61d2ca50 ("arm64: dts: qcom: fix pm8150 gpio interrupts"): qcs404-evb-4000.dtb: gpio@c000: 'interrupts' does not match any of the regexes: '-state$', 'pinctrl-[0-9]+' qcs404-evb-4000.dtb: gpio@c000: 'interrupt-controller' is a required property Signed-off-by:
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by:
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Krzysztof Kozlowski authored
The new Qualcomm PMIC GPIO bindings require gpio-ranges property: sm8250-sony-xperia-edo-pdx203.dtb: gpio@c000: 'gpio-ranges' is a required property Signed-off-by:
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- 27 Jun, 2022 29 commits
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Krzysztof Kozlowski authored
The CAMSS DTSI device node, which came after the bindings were merged, got the interrupts ordered differently then specified in the bindings: sdm630-sony-xperia-nile-pioneer.dtb: camss@ca00000: interrupt-names:0: 'csid0' was expected Reordering them to match bindings should not cause ABI issues, because the driver relies on names, not ordering. Signed-off-by:
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Krzysztof Kozlowski authored
The CAMSS DTSI device node, which came after the bindings were merged, got the regs ordered differently then specified in the bindings: sdm636-sony-xperia-ganges-mermaid.dtb: camss@ca00000: reg-names:0: 'csi_clk_mux' was expected Reordering them to match bindings should not cause ABI issues, because the driver relies on names, not ordering. Signed-off-by:
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Krzysztof Kozlowski authored
The CAMSS DTSI device node, which came after the bindings were merged, got the clocks ordered differently then specified in the bindings: sdm636-sony-xperia-ganges-mermaid.dtb: camss@ca00000: reg-names:4: 'csid3' was expected Reordering them to match bindings should not cause ABI issues, because the driver relies on names, not ordering. Signed-off-by:
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Krzysztof Kozlowski authored
The bindings require that every pin configuration comes with 'function' property. There is also no 'drive-strength' property but 'qcom,drive-strength': msm8994-msft-lumia-octagon-cityman.dtb: gpios@c000: amsel-high-state: 'oneOf' conditional failed, one must be fixed: 'drive-strength' does not match any of the regexes: 'pinctrl-[0-9]+' 'bias-pull-up', 'drive-strength', 'function', 'pins' do not match any of the regexes: '(pinconf|-pins)$', 'pinctrl-[0-9]+' Signed-off-by: -
Krzysztof Kozlowski authored
The bindings require that every pin configuration comes with 'function' property. Add such to PM8994 GPIO5. Signed-off-by:
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Krzysztof Kozlowski authored
The bindings require all PMIC GPIO nodes to have two compatibles - specific followed by SPMI or SSBI fallback. Add the fallback to fix warnings like: msm8916-samsung-serranove.dtb: gpios@c000: compatible: ['qcom,pm8916-gpio'] is too short Signed-off-by:
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Krzysztof Kozlowski authored
DT schema expects PMIC GPIO pin configuration nodes to be named with '-state' suffix. Optional children should be either 'pinconf' or followed with '-pins' suffix. This fixes dtbs_check warnings like: sdm845-xiaomi-beryllium.dtb: gpios@c000: 'vol-up-active' does not match any of the regexes: '-state$', 'pinctrl-[0-9]+' Signed-off-by:
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Marijn Suijten authored
2700000 is not a multiple of pmic4_pldo's step size of 8000 (with base voltage 1664000), resulting in pm8998-rpmh-regulators not probing. Just as we did with MSM8998's Sony Yoshino Poplar [1], round the voltages down to err on the cautious side and leave a comment in place to document this discrepancy wrt downstream sources. [1]: https://lore.kernel.org/linux-arm-msm/20220507153627.1478268-1-marijn.suijten@somainline.org/ Fixes: 30a7f99b ("arm64: dts: qcom: Add support for SONY Xperia XZ2 / XZ2C / XZ3 (Tama platform)") Signed-off-by:
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Konrad Dybcio authored
On MSM8996, the default bootloader configuration leaves the hosts in some weird state that never allows them to function properly under Linux. Add the hardware resets so that we can start clean and get them actually working. Signed-off-by:
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Konrad Dybcio authored
It looks like all Tone devices out in the wild are using PMI8996, which suggests the PMI8994-variant DTs are not needed. Remove them. Signed-off-by:
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Konrad Dybcio authored
Tone does not have a functioning bootloader framebuffer and Linux allocates the DRM framebuffer dynamically. Free up 36 MiB of precious RAM by removing this reservation. Signed-off-by:
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Konrad Dybcio authored
Merge the two DT files into one, sort the nodes and fix up a couple of style incoherencies by adding some newlines, removing some, sorting properties etc. Signed-off-by:
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Konrad Dybcio authored
While the Pro-1 is based on MTP and is very close to it, it's really not great for it to include the MTP dtsi straight up, as any small change will affect both boards and not all of them will apply to the phone as well. Signed-off-by:
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Konrad Dybcio authored
Sort the includes and remove unused ones. Signed-off-by:
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Konrad Dybcio authored
This is required to keep the display working with MMCC enabled until proper panel support is in place. Signed-off-by:
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Konrad Dybcio authored
MMCC is a component of the SoC that should always be configured. It was kept off due to misconfiguration on clamshell machines. Keep it disabled on these ones and enable it by default on all the others. Exactly the same story applies to MMSS_SMMU, which directly depends on MMCC. Do note, that if a platform doesn't use neither EFIFB (only applies to WoA devices in this case) or simplefb (applies to precisely 2 msm8998 devices as of this commit), this will not cause any harm. Signed-off-by:
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Konrad Dybcio authored
This is the standard way. Signed-off-by:
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Konrad Dybcio authored
Add some newlines, reorder some properties, remove some indentation to make it more coherent. Signed-off-by:
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Konrad Dybcio authored
Now that a label is added, use it! Signed-off-by:
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Konrad Dybcio authored
It's not necessary and the SoC clocks{} node doesn't use it either. Signed-off-by: -
Konrad Dybcio authored
While not strictly necessary, at least on maple, configure the USB extcon, which requires two pins on Yoshino. Signed-off-by:
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Konrad Dybcio authored
It's disabled on downstream, follow it. Signed-off-by:
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Konrad Dybcio authored
Reorder properties to match new laptop DTs, change hex to dec. Signed-off-by:
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Konrad Dybcio authored
Keep the nodes and includes in order, clean up unnecessary properties & nodes. Signed-off-by:
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Konrad Dybcio authored
Remove the unnecessary level of indentation, commonize SDC2 pins and notice that SDCC2_CD_ON and _OFF is identical, deduplicate it! Also, remove some unnecessary overrides and use decimal values in #-cells Signed-off-by:
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Bryan O'Donoghue authored
Add in the missing vdda-pll-supply rail description. Reviewed-by:
Robert Foss <robert.foss@linaro.org> Signed-off-by:
Bryan O'Donoghue <bryan.odonoghue@linaro.org> Signed-off-by:
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Bryan O'Donoghue authored
The dts entry vdda-supply connects to a common vdda-phy-supply rail. Rename to reflect what the functionality is. Reviewed-by:
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David Heidelberg authored
There's no reason the timer needs > 32-bits of address or size. Since we using 32-bit size, we need to define ranges properly. Fixes warnings as: ``` arch/arm64/boot/dts/qcom/sdm845-oneplus-fajita.dt.yaml: timer@17c90000: #size-cells:0:0: 1 was expected From schema: Documentation/devicetree/bindings/timer/arm,arch_timer_mmio.yaml ``` Signed-off-by:David Heidelberg <david@ixit.cz> Signed-off-by:
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Krzysztof Kozlowski authored
DT schema expects names of operating points tables to start with "opp-table": ipq6018-cp01-c1.dtb: cpu_opp_table: $nodename:0: 'cpu_opp_table' does not match '^opp-table(-[a-z0-9]+)?$' Use hyphens instead of underscores, fix the names to match DT schema or remove the prefix entirely when it is not needed. Signed-off-by:
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- 26 Jun, 2022 5 commits
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Vladimir Zapolskiy authored
At the moment there are no changes in SM8250 board files, which require camera clock controller to run, whenever it is needed for a particular board, the status of camcc device node will be changed in a board file. Signed-off-by:
Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org> Signed-off-by:
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Dmitry Baryshkov authored
As we are converting this platform to use DT clock bindings, add clocks and clock-names properties to the MMCC device tree node. Signed-off-by:
Stephen Boyd <sboyd@kernel.org> Signed-off-by:
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Dmitry Baryshkov authored
Add device tree node for uart20, which is typically used for Bluetooth attachment. Signed-off-by:
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Srinivasa Rao Mandadapu authored
Add pm7325 ldo_l17b regulator, which is required for wcd codec vdd buck supply on sc7280-qcard board. Signed-off-by:
Srinivasa Rao Mandadapu <quic_srivasam@quicinc.com> Co-developed-by:
Venkata Prasad Potturu <quic_potturu@quicinc.com> Signed-off-by:
Douglas Anderson <dianders@chromium.org> Reviewed-by:
Stephen Boyd <swboyd@chromium.org> Signed-off-by:
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Douglas Anderson authored
sc7280-herobrine based boards are specced to be able to access their SPI flash at 50 MHz with the drive strength of the pins set at 8. The drive strength is already set to 8 in "sc7280-herobrine.dtsi", so let's bump up the clock. The matching firmware change for this is at: https://review.coreboot.org/c/coreboot/+/63948 NOTE: the firmware change isn't _required_ to make the kernel work at 50 MHz, it merely shows that the boards are known to work fine at 50 MHz. ALSO NOTE: this doesn't update the "sc7280-chrome-common.dtsi" file which is used by both herobrine boards and IDP. At the moment the IDP boards aren't configuring a drive strength of 8 and it seems safer to just leave them at the slower speed if they're already working. Signed-off-by:
Matthias Kaehlcke <mka@chromium.org> Signed-off-by:
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