- 16 Oct, 2020 5 commits
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Chengming Gui authored
noretry = 0 cause some dGPU's kfd page fault tests fail, so set noretry to 1 for these special ASICs: vega20/navi10/navi14 v2: merge raven and default case due to the same setting v3: remove ARCTURUS Signed-off-by:
Chengming Gui <Jack.Gui@amd.com> Acked-by:
Felix Kuhling <Felix.Kuehling@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Huang Rui authored
This patch is to enable display IP block for vangogh platforms. Signed-off-by:
Huang Rui <ray.huang@amd.com> Reviewed-by:
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Huang Rui authored
DCN301 needs to use dmub create abm instance instead of dce. [ 1138.854204] BUG: kernel NULL pointer dereference, address: 0000000000000000 [ 1138.854206] #PF: supervisor instruction fetch in kernel mode [ 1138.854207] #PF: error_code(0x0010) - not-present page [ 1138.854208] PGD 0 P4D 0 [ 1138.854212] Oops: 0010 [#1] SMP NOPTI [ 1138.854216] CPU: 6 PID: 1240 Comm: modprobe Tainted: G W OE 5.9.0-rc2-custom #1 [ 1138.854217] Hardware name: AMD Chachani-VN/Chachani-VN, BIOS BAerithA104 10/01/2020 [ 1138.854221] RIP: 0010:0x0 [ 1138.854224] Code: Bad RIP value. [ 1138.854226] RSP: 0018:ffffc90001c4f638 EFLAGS: 00010286 [ 1138.854228] RAX: 0000000000000000 RBX: ffff88804f2b2800 RCX: ffffc90001c4f740 [ 1138.854229] RDX: 00000000000000e8 RSI: ffffc90001c4f640 RDI: ffff88805816f300 [ 1138.854230] RBP: ffffc90001c4f850 R08: ffffc90001c4f644 R09: ffffc90001c4f654 [ 1138.854231] R10: ffffc90001c4f72c R11: ffffc90001c4f740 R12: ffffc90001c4f640 [ 1138.854232] R13: ffffc90001c4f728 R14: 0000000000000000 R15: ffff888007296381 [ 1138.854235] FS: 00007f5f44d84540(0000) GS:ffff88805e380000(0000) knlGS:0000000000000000 [ 1138.854236] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [ 1138.854237] CR2: ffffffffffffffd6 CR3: 00000000194f4000 CR4: 0000000000050ee0 [ 1138.854239] Call Trace: [ 1138.854447] dmub_init_abm_config+0x220/0x267 [amdgpu] [ 1138.854654] dm_late_init+0x197/0x1ad [amdgpu] [ 1138.854846] ? dm_late_init+0x197/0x1ad [amdgpu] [ 1138.854999] amdgpu_device_ip_late_init+0x6f/0x21b [amdgpu] [ 1138.855148] amdgpu_device_init+0x1b7f/0x1cfb [amdgpu] [ 1138.855293] amdgpu_driver_load_kms+0x2c/0x26e [amdgpu] [ 1138.855437] amdgpu_pci_probe+0x1c7/0x249 [amdgpu] [ 1138.920489] local_pci_probe+0x48/0x80 [ 1138.920492] pci_device_probe+0x10f/0x1c0 Signed-off-by:
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Yifan Zhang authored
S/G (scatter/gather) display support for display buffers in system memory. Signed-off-by:
Yifan Zhang <yifan1.zhang@amd.com> Reviewed-by:
Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by:
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Yifan Zhang authored
[why] display S/G mode fails in Renoir [how] Setup system context in dm init. Signed-off-by:
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- 15 Oct, 2020 14 commits
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Mihir Bhogilal Patel authored
Create new debugfs entry to print memory info using VM buffer objects. V2: Added Common function for printing BO info. Dump more VM lists for evicted, moved, relocated, invalidated. Removed dumping VM mapped BOs. V3: Fixed coding style comments, renamed print API and variables. V4: Fixed coding style comments. Signed-off-by:Mihir Bhogilal Patel <Mihir.Patel@amd.com> Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
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Evan Quan authored
Current code wrongly treat all cases as job == NULL. Signed-off-by:
Evan Quan <evan.quan@amd.com> Reviewed-and-tested-by:
Jane Jian <Jane.Jian@amd.com> Signed-off-by:
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Likun Gao authored
Support to load RLC iram and dram ucode when RLC firmware struct use v2.2 Signed-off-by:
Likun Gao <Likun.Gao@amd.com> Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
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Likun Gao authored
Add function for sienna_cichlid to force PBB workload mode to zero by checking whether there have SE been harvested. Signed-off-by:
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Jiansong Chen authored
This reverts commit 39ad0824. TDR issue has been resovled by pmfw update. Signed-off-by:
Jiansong Chen <Jiansong.Chen@amd.com> Acked-by:
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Evan Quan authored
Disable/enable the GPO feature on UMD pstate entering/exiting. Signed-off-by:
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Evan Quan authored
Fulfill Navi gfx and pcie settings on umd pstate switching. V2: temporarily skip the pcie ASPM setting considering the ASPM function is not fully enabled yet Signed-off-by: -
Evan Quan authored
Enable Navi1X MGCG perfmon setting. Signed-off-by:
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Evan Quan authored
Support NAVI10 ASPM setting. Signed-off-by:
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Evan Quan authored
For entering UMD stable Pstate, the operations to enter rlc_safe mode, disable mgcg_perfmon and disable PCIE aspm are needed. And the opposite operations should be performed on UMD stable Pstate exiting. V2: take those ASICs(CI/SI/VI) which may not support this into consideration Signed-off-by: -
Evan Quan authored
Populate current link speed, width and clock domain frequency. Signed-off-by:
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Evan Quan authored
As for other clock domains. Signed-off-by:
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Huang Rui authored
This patch fixes the gfx hang while use firmware direct loading mode. Signed-off-by:
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Tom Rix authored
Representative checkpatch.pl warning WARNING: adding a line without newline at end of file 30: FILE: drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.h:30: +#endif Signed-off-by:
Tom Rix <trix@redhat.com> Signed-off-by:
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- 14 Oct, 2020 11 commits
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Alex Deucher authored
Fix this to avoid build problems if DRM_AMD_DC_DCN3_02 is defined, but DRM_AMD_DC_DCN3_01 is not. Fixes: 36d26912 ("drm/amd/display: Add support for DCN302 (v2)") Acked-by:
Nirmoy Das <nirmoy.das@amd.com> Acked-by:
Randy Dunlap <rdunlap@infradead.org> Reported-by:
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Kent Russell authored
Now that we use kvmalloc for the crat_image, we need to use kvfree when we destroy this. Fixes: d0e63b34 ("drm/amdkfd: Use kvmalloc instead of kmalloc for VCRAT") Reported-by:
Morris Zhang <shiwu.zhang@amd.clm> Signed-off-by:
Kent Russell <kent.russell@amd.com> Reviewed-by:
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Veerabadhran G authored
Synchronize the ring usage for vcn1 and jpeg1 to workaround a hardware bug. Signed-off-by:
Veerabadhran Gopalakrishnan <veerabadhran.gopalakrishnan@amd.com> Acked-by:
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Hawking Zhang authored
add mp0 11_0_12 for dimgrey_cavefish to the mem training supported list, otherwise the modeprobe would fail on dimgrey_cavefish with latest vbios. Signed-off-by:
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Huang Rui authored
The driver needn't load smu binary on APU platforms. Signed-off-by:
Kevin Wang <kevin1.wang@amd.com> Reviewed-by:
Madhav Chauhan <madhav.chauhan@amd.com> Signed-off-by:
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Evan Quan authored
To avoid underflow seen on Polaris10 with some 3440x1440 144Hz displays. As the threshold of 190 us cuts too close to minVBlankTime of 192 us. Signed-off-by:
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Mauro Carvalho Chehab authored
As reported by Sphinx: Documentation/gpu/amdgpu.rst:200: WARNING: Inline emphasis start-string without end-string. Signed-off-by:
Mauro Carvalho Chehab <mchehab+huawei@kernel.org> Signed-off-by:
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Mauro Carvalho Chehab authored
As warned when running "make htmldocs": ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h:345: warning: Function parameter or member 'force_timing_sync' not described in 'amdgpu_display_manager' This new struct member was not documented at kernel-doc markup. Fixes: 3d4e52d0 ("drm/amd/display: Add debugfs for forcing stream timing sync") Signed-off-by:
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Bernard Zhao authored
Functions (disable_all_writeback_pipes_for_stream & dc_enable_stereo & dc_post_update_surfaces_to_stream) always return true, there is no need to keep the return value. This change is to make the code a bit more readable. Signed-off-by:
Bernard Zhao <bernard@vivo.com> Signed-off-by:
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kernel test robot authored
drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.c:608:2-3: Unneeded semicolon Remove unneeded semicolon. Generated by: scripts/coccinelle/misc/semicolon.cocci Fixes: b4a7db71 ("drm/amdgpu: add per device user friendly xgmi events for vega20") CC: Jonathan Kim <jonathan.kim@amd.com> Signed-off-by:
kernel test robot <lkp@intel.com> Signed-off-by:
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Alex Deucher authored
GPU reset might get called during init time, before sw_init has been called. Reviewed-by:
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- 12 Oct, 2020 10 commits
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Roman Li authored
Display Manager support for green_sardine Signed-off-by:
Roman Li <Roman.Li@amd.com> Reviewed-by:
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Roman Li authored
Display Core support for green_sardine Signed-off-by:
Hersen Wu <hersenxs.wu@amd.com> Reviewed-by:
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Tao Zhou authored
Add DM block support for dimgrey_cavefish. Signed-off-by:
Tao Zhou <tao.zhou1@amd.com> Reviewed-by:
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Tao Zhou authored
dimgrey_cavefish has no ASD ucode currently, remove its initialization. Signed-off-by:
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Bhawanpreet Lakha authored
Handle CAVE_DIMGREY_CAVEFISH in amdgpu_dm v2: fix rebase typo (Alex) Signed-off-by:
Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by:
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Bhawanpreet Lakha authored
- add DCN302 resource, irq service, dmub loader, - handle DC_VERSION_DCN_3_02 - define DCN302 power gating functions - handle DCN302 in GPIO files - define I2C regs - add CONFIG_DRM_AMD_DC_DCN3_02 guard v2: rebase fixes (Alex) Signed-off-by:
Joshua Aberback <joshua.aberback@amd.com> Signed-off-by:
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Tao Zhou authored
Per PMFW 59.7.0. Signed-off-by:
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Tao Zhou authored
Remove gpu_info fw support for dimgrey_cavefish, gpu info can be got from ip discovery. Signed-off-by:
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Tao Zhou authored
Set ih CG flag for dimgrey_cavefish. Signed-off-by:
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Tao Zhou authored
Set hdp CG and LS flag for dimgrey_cavefish. Signed-off-by:
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