- 23 Dec, 2020 7 commits
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Martin Tsai authored
[why] The sink count change HPD_IRQ will be ignored if the branch device has only DP DFP. [how] To remove the port type restriction. Signed-off-by:
Martin Tsai <martin.tsai@amd.com> Acked-by:
Bindu Ramamurthy <bindu.r@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Martin Tsai authored
[why] Some MST display may not report the internal panel to DEVICE_COUNT, that makes the check condition always failed. [how] To update this condition with the reported device count + 1 (because the immediate repeater's internal panel is possibly not included in DEVICE_COUNT) Signed-off-by:
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Wesley Chalmers authored
[WHY] HUBP blanking sequence on DCN30 requires us to check if HUBP is in blank and also toggle HUBP_DISABLE, which should instead be called HUBP_SOFT_RESET for what it does in HW. Signed-off-by:
Wesley Chalmers <Wesley.Chalmers@amd.com> Acked-by:
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Qingqing Zhuo authored
[why] handler is supposedly passed in as a function pointer; however, the entire struct amdgpu_dm_irq_handler_data gets from the list is used to check match. [how] use the interrupt_handler within amdgpu_dm_irq_handler_data for checking match. Signed-off-by:
Qingqing Zhuo <qingqing.zhuo@amd.com> Acked-by:
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Hawking Zhang authored
GUI_IDLE interrupts controlled by CP_INT_CNTL_RING0 are only applicable to me0 pipe0. For ASICs that have gfx pipe removed, don't toggle those bits. Signed-off-by:
Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by:
Feifei Xu <Feifei.Xu@amd.com> Reviewed-by:
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Hawking Zhang authored
The number of crtc should be 0 for ASICs that don't have display engine. Remove the unnecessary asic type check then. Signed-off-by:
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Hawking Zhang authored
Check number of gfx ring, rather than asic type, before cp gfx engine initialization so driver just need to make sure number of gfx ring is initialized correctly in gfx early_init phase. No need to add additional asic type check everywhere when there is new asic with gfx pipe removed. Signed-off-by:
Christian König <christian.koenig@amd.com> Reviewed-by:
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- 17 Dec, 2020 3 commits
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Alex Deucher authored
There is no reserveration so set the size to 0. Fixes a regression on SR-IOV. Reviewed-by:
Guchun Chen <guchun.chen@amd.com> Signed-off-by:
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Xiaomeng Hou authored
Only pmfw version behind v4.63.23.00 could support this message. Signed-off-by:
Xiaomeng Hou <Xiaomeng.Hou@amd.com> Reviewed-by:
Huang Rui <ray.huang@amd.com> Signed-off-by:
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Harish Kasiviswanathan authored
GFX10 CP firmware expects PCIe atomics support. Don't enumerate GFX10 devices on platforms (PCIe v2) that don't support PCIe atomics. Currently, some of the applications like clinfo soft hangs on platforms without PCIe atomics support. Signed-off-by:
Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com> Reviewed-by:
Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by:
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- 16 Dec, 2020 4 commits
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Alex Deucher authored
Add documentation for crc window. Fixes: c920888c ("drm/amd/display: Expose new CRC window property") Signed-off-by:
Stephen Rothwell <sfr@canb.auug.org.au> Reviewed-by:
Wayne Lin <Wayne.Lin@amd.com>
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Tao Zhou authored
This makes it easier to debug what block is causing the fault, same as sienna_cichlid. Signed-off-by:
Tao Zhou <tao.zhou1@amd.com> Reviewed-by:
Jiansong Chen <Jiansong.Chen@amd.com> Signed-off-by:
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Tao Zhou authored
Use mode1 reset for dimgrey_cavefish by default. Signed-off-by:
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Rodrigo Siqueira authored
Some old ASICs might not implement/require get_dig_frontend helper; in this scenario, we can have a NULL pointer exception when we try to call it inside vbios disable operation. For example, this situation might happen when using Polaris12 with an eDP panel. This commit avoids this situation by adding a specific get_dig_frontend implementation for DCEx. Cc: Alex Deucher <alexander.deucher@amd.com> Cc: Borislav Petkov <bp@alien8.de> Cc: Harry Wentland <Harry.Wentland@amd.com> Cc: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Cc: Chiawen Huang <chiawen.huang@amd.com> Reported-and-tested-by:
Borislav Petkov <bp@suse.de> Acked-by:
Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by:
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- 15 Dec, 2020 26 commits
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Tom Rix authored
See Documentation/core-api/printk-formats.rst. h should no longer be used in the format specifier for printk. Reviewed-by:
Tom Rix <trix@redhat.com> Signed-off-by:
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Tom Rix authored
See Documentation/core-api/printk-formats.rst. h should no longer be used in the format specifier for printk. Reviewed-by:
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Colin Ian King authored
There is a spelling mistake in a comment in the Kconfig. Fix it. Signed-off-by:
Colin Ian King <colin.king@canonical.com> Signed-off-by:
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Alex Deucher authored
We need to move the check under the non-headless case, otherwise we always reserve the VGA save size. Fixes: 157fe68d ("drm/amdgpu: fix size calculation with stolen vga memory") Reviewed-by:
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Jiange Zhao authored
In Virtualization case, when one VF is sending too many FLR requests, hypervisor would stop responding to this VF's request for a long period of time. This is called event guard. During this period of cooling time, guest driver should wait instead of doing other things. After this period of time, guest driver would resume reset process and return to normal. Currently, guest driver would wait 12 seconds and return fail if it doesn't get response from host. Solution: extend this waiting time in guest driver and poll response periodically. Poll happens every 6 seconds and it will last for 60 seconds. v2: change the max repetition times from number to macro. Signed-off-by:
Jiange Zhao <Jiange.Zhao@amd.com> Acked-by:
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Yifan Zhang authored
it could also be insufficient vram that makes amdgpu_amdkfd_reserve_mem_limit fail. Signed-off-by:
Yifan Zhang <yifan1.zhang@amd.com> Reviewed-by:
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Souptick Joarder authored
Kernel test robot throws below warning -> drivers/gpu/drm/amd/amdgpu/../display/dc/dcn21/dcn21_dccg.c:46:6: warning: no previous prototype for 'dccg21_update_dpp_dto' [-Wmissing-prototypes] Adding prototype for dccg21_update_dpp_dto(). Reported-by:
kernel test robot <lkp@intel.com> Signed-off-by:
Souptick Joarder <jrdr.linux@gmail.com> Signed-off-by:
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Alex Deucher authored
So we know when it's enabled and what method we are using. Acked-by:
Evan Quan <evan.quan@amd.com> Signed-off-by:
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Alex Deucher authored
Simplify the logic in the runtime resume handling for atpx Acked-by:
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Alex Deucher authored
The platform knows it's doing d3cold. Acked-by:
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Alex Deucher authored
Enable runtime pm on non HG/PX BOCO capable boards. Acked-by:
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Alex Deucher authored
Change it to check if the device has ACPI power resources. Acked-by:
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Alex Deucher authored
Check if the device has ACPI power resources so we can enable runtime pm if so. Acked-by:
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Alex Deucher authored
In preparation for systems that support d3cold on dGPUs independent of PX/HG. No functional change intended. Acked-by:
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Souptick Joarder authored
Kernel test robot throws below warning -> drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:5349:5: warning: no previous prototype for 'amdgpu_dm_crtc_atomic_set_property' [-Wmissing-prototypes] drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:5349:5: warning: no previous prototype for function 'amdgpu_dm_crtc_atomic_set_property' [-Wmissing-prototypes] drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:5373:5: warning: no previous prototype for 'amdgpu_dm_crtc_atomic_get_property' [-Wmissing-prototypes] drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:5373:5: warning: no previous prototype for function 'amdgpu_dm_crtc_atomic_get_property' [-Wmissing-prototypes] As these functions are only used inside amdgpu_dm.c, these can be made static. Reported-by:
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Aric Cyr authored
Signed-off-by:
Aric Cyr <aric.cyr@amd.com> Acked-by:
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Anthony Koo authored
- Add new aux_channel_type - Changed port_index to instance in dmub_cmd_dp_aux_control_data - Change aux_return_code_type to sync up with driver - param for ramping abm based on backlight level Signed-off-by:
Anthony Koo <Anthony.Koo@amd.com> Acked-by:
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Aric Cyr authored
[Why] Typo in MPCC visual confirmation. [How] Fix to correct values. Signed-off-by:
Jun Lei <Jun.Lei@amd.com> Acked-by:
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Felipe authored
[Why] The OGAM LUT precision was accumulating too much error in the higher end. [How] Instead of calculating all points of the LUT in relation to the previous ones, perform a full calculation in one of the intermediate segments to stop error propagation. Signed-off-by:
Felipe Clark <Felipe.Clark@amd.com> Reviewed-by:
Krunoslav Kovac <Krunoslav.Kovac@amd.com> Acked-by:
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Aric Cyr authored
[Why] FP2 is not double buffered and must wait for VACTIVE before programming. [How] Only update when there is a full update we should change FP2 to avoid delay every flip. Signed-off-by:
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Jake Wang authored
[Why] For certain timings, Renoir may underflow due to sr exit latency being too slow. [How] Updated wm table for renoir. Signed-off-by:
Jake Wang <haonan.wang2@amd.com> Reviewed-by:
Yongqiang Sun <yongqiang.sun@amd.com> Acked-by:
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Martin Leung authored
[Why] race condition of programming FP2 wrt pipe locking and vactive state can cause underflow/black screen [How] Enforce the FP2 is only programmed during vactive, and unlock pipe soon afterwards. Signed-off-by:
Martin Leung <martin.leung@amd.com> Reviewed-by:
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Leo (Hanghong) Ma authored
[Why] We are missing the DP info frame update on dcn30, and this will lead to DP SDPs not being sent; [How] Add the DP info frame update for dcn30; Signed-off-by:
Leo (Hanghong) Ma <hanghong.ma@amd.com> Reviewed-by:
Roman Li <Roman.Li@amd.com> Acked-by:
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Eric Bernstein authored
[Why] dcn30_link_encoder_validate_output_with_stream was a static function. [How] remove the static define and include it in the header. Signed-off-by:
Eric Bernstein <eric.bernstein@amd.com> Reviewed-by:
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by:
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Wayne Lin authored
[Why] Find out when we try to disable CRC calculation, crc generation is still enabled. Main reason is that dc_stream_configure_crc() will never get called when the source is AMDGPU_DM_PIPE_CRC_SOURCE_NONE. [How] Add checking condition that when source is AMDGPU_DM_PIPE_CRC_SOURCE_NONE, we should also call dc_stream_configure_crc() to disable crc calculation. Also, clean up crc window when disable crc calculation. Signed-off-by:
Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by:
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Aric Cyr authored
[Why] Many VR headsets require a HSYNC width of 4, but DCN has default minimum of 8. [How] Change the arbitrary minimum HSYNC width to 4 to match DCN20. Signed-off-by:
Charlene Liu <Charlene.Liu@amd.com> Reviewed-by:
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